How to make LLCE_CAN work on M7 for multiboot (M7/A53)

[Namic]

Hi,

I use Can_llce_DS_Loopback example and run on M7 and configure LINFlexD_1 to output UART log.

It can run normally only on M7_0.

1. I refer to S32G_Bootloader_V2-2022.1024_eng.pdf to configure bootloader and M7 app (Remove Mcu_Init(), Port_Init(), Platform_Init()).
2. Enable the interrupt for UART1 and LLCE_CAN (LINFLEXD1_IRQn/LLCE0_ICSR14_IRQn/LLCE0_ICSR15_IRQn/LLCE0_ICSR16_IRQn/LLCE0_ICSR17_IRQn/LLCE0_ICSR22_IRQn/LLCE0_ICSR23_IRQn).
3. Configure clock for MCU configuration of M7 app and bootloader.
4. Modify linker_ram.ld. Change the region of int_sram to 0x34000000.
5. On A53, remove llce_can.config and llce_logger.config (LinuxBSP_35).

When booting, if I enter uboot, the M7 can run LLCE_CAN loopback example normally.

If A53 is booting into OS, the M7 will stop unexpectedly.

Here are my Questions:

1. What configurations do I check for M7 run normally ?
2. Does it possible to let LLCE_CAN controller 0-7 run on M7 and controller 8-15 run on A53 simultaneously ?

Thanks.

[ShenYi]

Hi,

   I have the same problem. Have you solved this problem?

[Daniel-Aguirre]

Hi,

The following is provided from our internal team:

"This case has been tested on BSP30(A53) and LLCE 1.0.1(M7)

For example, resource LLCE CAN0-CAN7 assigned to M7_0 core, and resource LLCE CAN8-CAN15 assigned to A53 cores

Precondition

• Multiple core boot is ok, and M7 application runs faster than Linux kernel.
• CAN_PE clock shall be the same both on M7 and A53 sides.

M7 side:

• Load fw on the M7 side not A53
• Disable interrupt of LLCE CAN8 ~ LLCE CAN15

• Modify the ‘PlatformInitConfig0_PB’ corresponding to ‘llce_platform_init’

PlatformInitConfig0_PB:

llce_platform_init

A53 side:

• Enable LLCE CAN feature and specify the location where firmware binaries:

• Disable firmware loading:

~/build_s32g274ardb2/tmp/work/s32g274ardb2-fsl-linux/linux-s32/5.10.41-r0/git/drivers/mfd/llce-core.c

• Comment ‘llce_platform_init’

~/build_s32g274ardb2/tmp/work/s32g274ardb2-fsl-linux/linux-s32/5.10.41-r0/git/drivers/mailbox/llce-mailbox.c

• Disable interrupt of LLCE CAN0 ~ LLCE CAN7

~/build_s32g274ardb2/tmp/work/s32g274ardb2-fsl-linux/linux-s32/5.10.41-r0/git/drivers/mailbox/llce-mailbox.c

"

Please, let us know.

[Namic]

Hi,

Thanks for your replies.

I used BSP35(A53) and LLCE 1.0.4(M7).

I follow the steps to modify the CAN_PE_CLK on M7 and llce-core.c and llce-mailbox.c on A53.

I also remove LLCE_CAN0~8 and LLCE_CAN11~15 in kernel dtsi file.

I run LLCE_CAN0/LLCE_CAN1 on M7 and enable LLCE_CAN9/LLCE_CAN10 on A53.

The M7 app would stop when A53 booting to login.

What configurations do I missing?

Thanks.

[Daniel-Aguirre]

Hi,

Thanks for your feedback.

Did you disable the loading of LLCE from Linux side? We did not see it mentioned under the steps you followed.

Please, let us know.

[Namic]

Hi,

Yes, I have disabled LLCE on A53 side.

Please check below changes:

diff --git a/drivers/mailbox/llce-mailbox.c b/drivers/mailbox/llce-mailbox.c
index 87955a60c0f0..ef16d2713636 100644
--- a/drivers/mailbox/llce-mailbox.c
+++ b/drivers/mailbox/llce-mailbox.c
@@ -736,9 +736,9 @@ static int request_llce_pair_irq(struct llce_mb *mb, struct llce_pair_irq *pair)
 {
        int ret;

-       ret = request_llce_irq(mb, &pair->irq0);
-       if (ret)
-               return ret;
+       // ret = request_llce_irq(mb, &pair->irq0);
+       // if (ret)
+       //      return ret;

        ret = request_llce_irq(mb, &pair->irq8);
        if (ret)
@@ -1982,11 +1982,11 @@ static int llce_mb_probe(struct platform_device *pdev)

        fw_logger_support(mb, &ver);

-       ret = llce_platform_init(dev, mb);
-       if (ret) {
-               dev_err(dev, "Failed to initialize platform\n");
-               goto disable_clk;
-       }
+       // ret = llce_platform_init(dev, mb);
+       // if (ret) {
+       //      dev_err(dev, "Failed to initialize platform\n");
+       //      goto disable_clk;
+       // }

        ret = devm_mbox_controller_register(dev, ctrl);
        if (ret < 0) {
diff --git a/drivers/mfd/llce-core.c b/drivers/mfd/llce-core.c
index a9fe41b25d47..0207aff9632d 100644
--- a/drivers/mfd/llce-core.c
+++ b/drivers/mfd/llce-core.c
@@ -61,7 +61,8 @@ struct llce_core {
        size_t nfrws;
 };

-static bool load_fw = true;
+// static bool load_fw = true;
+static bool load_fw = false;
 module_param(load_fw, bool, 0660);

 static struct device_node *get_sram_node(struct device *dev, const char *name)

[Daniel-Aguirre]

Hi,

Thanks for your feedback. Does this happen if you also load a simple blink example with PA_06??

If so, could be that the dtb has not been modified to not map the pins that the M7 is going to use.

Also, we were looking that you said the following:

"Modify linker_ram.ld. Change the region of int_sram to 0x34000000."

It means, that you leave the example as it is? Did you not follow the modification mentioned over "S32G_Bootloader_V2-2022.1024_eng.pdf "?.

Please, let us know.

[Namic]

Hi,

I don't load the sample blink example with PA_06.

But I used the UART1 example with multiboot, and it can work well.

For linker_ram.ld, I followed the "S32G_Bootloader_V2-2022.1024_eng.pdf" to modify and M7 app cannot run.

I modified it as below picture and M7 app with UART1 example can work normally.

But I used LLCE_CAN example, the M7 app would stop unexpectedly during A53 booting.

Thanks.

[Daniel-Aguirre]

Hi,

If the above still does not work, we have received the following notice from our internal team:

"LLCE CAN multi-host support will be added to Linux BSP37"

We do apologize.

Please, let us know.

[Namic]

Hi,

For the linux BSP37, when can I download it ?

Thanks.

[Daniel-Aguirre]

Hi,

For what we can see, it seems to be planned sometime in 2023 Q3. This can be moved into Q4 if required but seems Q3 is the plan.

If more information is required on this regard, help us contact your local NXP FAE, for them to provide you with the required release once it is available.

Please, let us know.