Hello experts
I have another question about the clock of PFE module, as follow:
We referred to the GMAC driver’s clock configuration in the existing RTOS BSP. When initializing the PFE module, it is necessary to configure the MC_CGM_2 register block—specifically, to set up the TX clock for PFE_MAC_0, we need to configure the Clock Mux 1 Select Control Register (MUX_1_CSC) within this register group, as shown in the figure below.

In the SELCTL field of this register, a clock source must be selected. However, we are unsure how the clk_src_x identifiers described in the reference manual correspond to the actual hardware clock sources.

We found some related descriptions in the device tree files, but we don’t know how to map them correctly. Could you please clarify how clk_src_x in the manual relates to the real clock sources used in the system?