We designed our custom board based on S32G274A, and the board SDRAM size is 512MB.
So we change the memory size to 0x20000000H in arch/arm/dts/fsl-s32g274a.dtsi in uboot base on bsp31.0_5.4_cd-2020.04.
diff --git a/arch/arm/dts/fsl-s32g274a.dtsi b/arch/arm/dts/fsl-s32g274a.dtsi
index 0318680155..7a326f4799 100644
--- a/arch/arm/dts/fsl-s32g274a.dtsi
+++ b/arch/arm/dts/fsl-s32g274a.dtsi
@@ -14,16 +14,25 @@
compatible = "fsl,s32g274-simu", "fsl,s32g274", "fsl,s32gen1",
"arm,vexpress,v2p-aarch64", "arm,vexpress";
+#if 0
memory@80000000 {
device_type = "memory";
reg = <0 0x80000000 0 0x80000000>;
};
+
memory@880000000 {
device_type = "memory";
reg = <0x8 0x80000000 0 0x80000000>;
};
+#else
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0x20000000>;
+ };
+#endif
sram@34000000 {
device_type = "memory";
reg = <0 0x34000000 0 0x800000>;
But when the uboot starts, we will prompt this err information:
U-Boot 2020.04-dirty (Dec 06 2022 - 18:30:16 +0800)
CPU: NXP S32G274A rev. 2.1.0
Reset cause: Power-On Reset
Model: NXP S32G2XX
Board: NXP S32G274A-RDB
DRAM: Error 3 on ddr_init
initcall sequence 0000000034104548 failed at call 00000000340a2c58 (err=3)
### ERROR ### Please RESET the board ###
So we made the following changes and add debugging information in uboot source code.The patch is here:
diff --git a/arch/arm/dts/fsl-s32g274a.dtsi b/arch/arm/dts/fsl-s32g274a.dtsi
index 0318680155..7a326f4799 100644
--- a/arch/arm/dts/fsl-s32g274a.dtsi
+++ b/arch/arm/dts/fsl-s32g274a.dtsi
@@ -14,16 +14,25 @@
compatible = "fsl,s32g274-simu", "fsl,s32g274", "fsl,s32gen1",
"arm,vexpress,v2p-aarch64", "arm,vexpress";
+#if 0
memory@80000000 {
device_type = "memory";
reg = <0 0x80000000 0 0x80000000>;
};
+
memory@880000000 {
device_type = "memory";
reg = <0x8 0x80000000 0 0x80000000>;
};
+#else
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0x20000000>;
+ };
+#endif
sram@34000000 {
device_type = "memory";
reg = <0 0x34000000 0 0x800000>;
diff --git a/board/freescale/s32-gen1/ddr_init.c b/board/freescale/s32-gen1/ddr_init.c
index 3eedf50866..9e0301946c 100644
--- a/board/freescale/s32-gen1/ddr_init.c
+++ b/board/freescale/s32-gen1/ddr_init.c
@@ -47,22 +47,26 @@ u32 ddr_init(void)
for (i = 0; i < ddrss_config_size; i++) {
/* Init DDR controller based on selected parameter values */
ret = ddrc_init_cfg(&configs[i]);
+ printf("[DEBUG1]i=%d , ret = %d\n",i,ret);
if (ret != NO_ERR)
return ret;
/* Setup AXI ports parity */
ret = set_axi_parity();
+printf("[DEBUG2]i=%d , ret = %d\n",i,ret);
if (ret != NO_ERR)
return ret;
/* Init PHY module */
ret = execute_training(&configs[i]);
+printf("[DEBUG3]i=%d , ret = %d\n",i,ret);
if (ret != NO_ERR)
return ret;
/* Execute post training setup */
ret = post_train_setup((u8)(STORE_CSR_MASK |
INIT_MEM_MASK));
+printf("[DEBUG4]i=%d , ret = %d\n",i,ret);
if (ret != NO_ERR)
return ret;
}
@@ -84,11 +88,16 @@ static u32 execute_training(const struct ddrss_config *config)
u32 ret = NO_ERR;
/* Apply DQ swapping settings */
ret = load_dq_cfg(config->dq_swap_size, config->dq_swap);
+
+ printf("[execute_training DEBUG 1 ] ret = %d\n",ret);
+
if (ret != NO_ERR)
return ret;
/* Initialize phy module */
ret = load_register_cfg_16(config->phy_size, config->phy);
+ printf("[execute_training DEBUG 2 ] ret = %d\n",ret);
+
if (ret != NO_ERR)
return ret;
@@ -96,6 +105,8 @@ static u32 execute_training(const struct ddrss_config *config)
writel(UNLOCK_CSR_ACCESS, MICROCONT_MUX_SEL);
ret = load_phy_image(IMEM_START_ADDR, config->imem_1d_size,
config->imem_1d);
+printf("[execute_training DEBUG 3 ] ret = %d\n",ret);
+
if (ret != NO_ERR)
return ret;
writel(LOCK_CSR_ACCESS, MICROCONT_MUX_SEL);
@@ -104,6 +115,8 @@ static u32 execute_training(const struct ddrss_config *config)
writel(UNLOCK_CSR_ACCESS, MICROCONT_MUX_SEL);
ret = load_phy_image(DMEM_START_ADDR, config->dmem_1d_size,
config->dmem_1d);
+printf("[execute_training DEBUG 4 ] ret = %d\n",ret);
+
if (ret != NO_ERR)
return ret;
writel(LOCK_CSR_ACCESS, MICROCONT_MUX_SEL);
@@ -117,6 +130,7 @@ static u32 execute_training(const struct ddrss_config *config)
writel(APBONLY_MICRORESET_CLR_MASK, APBONLY_MICRORESET);
ret = wait_firmware_execution();
+ printf("[execute_training DEBUG 5 ] ret = %d\n",ret);
writel(UNLOCK_CSR_ACCESS, MICROCONT_MUX_SEL);
if (ret != NO_ERR)
return ret;
@@ -130,6 +144,7 @@ static u32 execute_training(const struct ddrss_config *config)
writel(UNLOCK_CSR_ACCESS, MICROCONT_MUX_SEL);
ret = load_phy_image(IMEM_START_ADDR, config->imem_2d_size,
config->imem_2d);
+printf("[execute_training DEBUG 6 ] ret = %d\n",ret);
if (ret != NO_ERR)
return ret;
writel(LOCK_CSR_ACCESS, MICROCONT_MUX_SEL);
@@ -138,6 +153,7 @@ static u32 execute_training(const struct ddrss_config *config)
writel(UNLOCK_CSR_ACCESS, MICROCONT_MUX_SEL);
ret = load_phy_image(DMEM_START_ADDR, config->dmem_2d_size,
config->dmem_2d);
+printf("[execute_training DEBUG 7 ] ret = %d\n",ret);
if (ret != NO_ERR)
return ret;
writel(LOCK_CSR_ACCESS, MICROCONT_MUX_SEL);
@@ -151,6 +167,7 @@ static u32 execute_training(const struct ddrss_config *config)
writel(APBONLY_MICRORESET_CLR_MASK, APBONLY_MICRORESET);
ret = wait_firmware_execution();
+printf("[execute_training DEBUG 8 ] ret = %d\n",ret);
if (ret != NO_ERR)
return ret;
}
@@ -158,6 +175,8 @@ static u32 execute_training(const struct ddrss_config *config)
writel(UNLOCK_CSR_ACCESS, MICROCONT_MUX_SEL);
/* Load pie image after training has executed */
ret = load_register_cfg_16(config->pie_size, config->pie);
+printf("[execute_training DEBUG 9 ] ret = %d\n",ret);
+
writel(LOCK_CSR_ACCESS, MICROCONT_MUX_SEL);
return ret;
}
diff --git a/board/freescale/s32-gen1/ddr_utils.c b/board/freescale/s32-gen1/ddr_utils.c
index a658f80999..98db8317a8 100644
--- a/board/freescale/s32-gen1/ddr_utils.c
+++ b/board/freescale/s32-gen1/ddr_utils.c
@@ -340,7 +340,8 @@ u32 wait_firmware_execution(void)
while ((mail != TRAINING_OK_MSG) && (ret == NO_ERR)) {
ret = get_mail(&mail);
-
+
+ printf("[wait_firmware_execution DEBUG]ret=%d, mail=%d \n",ret, mail);
/* 0x07 means OK, 0xFF means failure */
if (mail == TRAINING_FAILED_MSG) {
/* Training stage failed */
@@ -378,15 +379,21 @@ static u32 get_mail(u32 *mail)
u32 timeout = DEFAULT_TIMEOUT;
u32 tmp32 = readl(DDR_PHYA_APBONLY_UCTSHADOWREGS);
+ printf("[get_mail DEBUG 1 ]tmp32=%08X \n",tmp32);
+
while ((--timeout != 0u) && ((tmp32 & UCT_WRITE_PROT_SHADOW_MASK) !=
UCT_WRITE_PROT_SHADOW_ACK))
tmp32 = readl(DDR_PHYA_APBONLY_UCTSHADOWREGS);
+
+ printf("[get_mail DEBUG 2 ]tmp32=%08X ,timeout=%X\n",tmp32, timeout);
if (timeout == 0u)
return TIMEOUT_ERR;
*mail = readl(DDR_PHYA_APBONLY_UCTWRITEONLYSHADOW);
-
+
+ printf("[get_mail DEBUG 3 ]*mail=%X\n",*mail);
+
/* ACK */
return ack_mail();
}
diff --git a/include/common.h b/include/common.h
index 8ffcdae54c..c73c36e4d6 100644
--- a/include/common.h
+++ b/include/common.h
@@ -48,4 +48,15 @@
# include <env_internal.h>
#endif
+
+
+
+#define DEBUG
+
+#ifdef DEBUG
+#define _DEBUG 1
+#else
+#define _DEBUG 0
+#endif
+
#endif /* __COMMON_H_ */
After that ,uboot log is here:
U-Boot 2020.04-dirty (Dec 06 2022 - 19:05:11 +0800)
CPU: NXP S32G274A rev. 2.1.0
Reset cause: Power-On Reset
Model: NXP S32G2XX
Board: NXP S32G274A-RDB
DRAM: initcall: 00000000340a2e88
[DEBUG1]i=0 , ret = 0
[DEBUG2]i=0 , ret = 0
[execute_training DEBUG 1 ] ret = 0
[execute_training DEBUG 2 ] ret = 0
[execute_training DEBUG 3 ] ret = 0
[execute_training DEBUG 4 ] ret = 0
[get_mail DEBUG 1 ]tmp32=00000003
[get_mail DEBUG 2 ]tmp32=00000002 ,timeout=F3C7F
[get_mail DEBUG 3 ]*mail=FF
[wait_firmware_execution DEBUG]ret=0, mail=255
[execute_training DEBUG 5 ] ret = 3
[DEBUG3]i=0 , ret = 3
Error 3 on ddr_init
initcall sequence 000000003410a598 failed at call 00000000340a2e88 (err=3)
### ERROR ### Please RESET the board ###
SandalHao_1-1670326011575.png
SandalHao_1-1670326297430.png
From the comment information, we can see that the error return value 3 is due to the register DDR_PHYA_APBONLY_UCTWRITEONLYSHADOW's value is 0xFF.
So I want to ask NXP experts, what might be the cause?How do I do?