Dynamic configuration in sja1110

[Atkinson]

Hi, 

I would like to configure l2 lookup table dynamically how can I configure it ?

Without using ECT tool how can I configure the l2 lookup table ? 

Any examples?

Regards 

Atkinson

[Atkinson]

Hi @PavelL 

1.) So this change of accessing the register for Dynamic configuration need to be done in S32G or SJA1110 switch ?
2.)if via SJA1110 switch whether reading and writing the register by SPI need to be performed and where this implementation need to be carried in between SWITCH_DRV?
3.) where we can create our Dynamic entry so that it will get append in switch 

More Explanation would be great help!!

[PavelL]

Hello @Atkinson ,

Answers to your question are related to your application use case.

You can create a dynamic entry absolutely anywhere, also in S32G or in SJA1110:

• transfer the entry in any supported way to the S32G and write it to SJA1110 via SPI, or via Ethernet
• or, transfer the entry to the SJA1110 via Ethernet and use internal AHB access
• or, send a custom trigger event (GPIO, Ethernet frame, ...) to the SJA1110, create a dynamic entry there and write the entry via AHB access
• or, ....
• or, ....

There are examples how to write dynamic entry to the switchcore of SJA1110:

• via SPI - python script write_l2_lookup_table.py
• via AHB - source code of ECT server

Bets regards,

Pavel

[Atkinson]

Hi @PavelL 

#define L2_ENTRY0_ADDR 0xFF00008c
#define L2_ENTRY1_ADDR 0xFF000090
#define L2_ENTRY2_ADDR 0xFF000094
#define L2_ENTRY3_ADDR 0xFF000098
#define L2_ENTRY4_ADDR 0xFF00009C
#define L2_ENTRY5_ADDR 0xFF0000A0
#define L2_CTRL_ADDR 0xFF0000A4
Std_ReturnType CreateL2Entry(uint32_t entry[6])
{
uint16_t INDEX = 11;
uint64_t MACADDR = 0x661122334455;
uint64_t MACADDR_MASK = 0xFFFFFFFFFFFF;
uint16_t VLANID = 3;
uint16_t VLANID_MASK = 0xFFF;
uint8_t IOTAG = 0;
uint8_t IOTAG_MASK = 0;
uint8_t SRCPORT = 5;
uint8_t SRCPORT_MASK = 0xF;
uint8_t DESTPORTS = 0x02;
uint8_t ENFPORT = 1;
uint8_t RETAG = 0;
uint8_t MIRROR = 0;
uint8_t TAKETS = 0;
uint16_t MIRR_VLAN = 0xFFF;
uint8_t TRAPTOHOST = 0;
uint8_t CBSIDIN = 0x3F;
uint8_t CBENONDA = 0;
uint16_t VLIDX = 0xFFF;
uint8_t SA_POLICE = 0;
uint8_t DA_POLICE = 0;

entry[0] = ((INDEX & 0x03FF) << 1) |
((ENFPORT & 0x1) << 11) |
((DESTPORTS & 0x7FF) << 12) |
((SRCPORT & 0xF) << 23) |
((MACADDR & 0x1F) << 27);

entry[1] = (uint32_t)((MACADDR >> 5) & 0xFFFFFFFF);

entry[2] = (((MACADDR >> 37) & 0x7FF) << 0) |
((VLANID & 0xFFF) << 11) |
((IOTAG & 0x1) << 23) |
((MACADDR_MASK & 0xFF) << 24);

entry[3] = (uint32_t)((MACADDR_MASK >> & 0xFFFFFFFF);

entry[4] = (((MACADDR_MASK >> 40) & 0xFF) << 0) |
((VLANID_MASK & 0xFFF) << |
((IOTAG_MASK & 0x1) << 20) |
((SRCPORT_MASK & 0xF) << 21) |
((RETAG & 0x1) << 25) |
((MIRROR & 0x1) << 26) |
((TAKETS & 0x1) << 27) |
((MIRR_VLAN & 0xF) << 28);

entry[5] = (((MIRR_VLAN >> 4) & 0xFF) << 0) |
((TRAPTOHOST & 0x1) << |
((CBSIDIN & 0x3F) << 9) |
((CBENONDA & 0x1) << 15) |
((VLIDX & 0xFFF) << 17) |
((SA_POLICE & 0x1) << 29) |
((DA_POLICE & 0x1) << 30);

return E_OK;
}

Std_ReturnType WriteL2LookupEntry(uint8_t swt)
{
if (swt > 0) return E_NOT_OK;

Std_ReturnType ret;
uint32_t ctrlReg = 0;
uint32_t entry[6];

ret = CreateL2Entry(entry);
if (ret != E_OK) return ret;

do {
ret = spi_read_reg(L2_CTRL_ADDR, &ctrlReg);
if (ret != E_OK) return ret;
} while (ctrlReg & (1U << 31));

ret = spi_write_reg(L2_ENTRY0_ADDR, entry[0]); if (ret != E_OK) return ret;
ret = spi_write_reg(L2_ENTRY1_ADDR, entry[1]); if (ret != E_OK) return ret;
ret = spi_write_reg(L2_ENTRY2_ADDR, entry[2]); if (ret != E_OK) return ret;
ret = spi_write_reg(L2_ENTRY3_ADDR, entry[3]); if (ret != E_OK) return ret;
ret = spi_write_reg(L2_ENTRY4_ADDR, entry[4]); if (ret != E_OK) return ret;
ret = spi_write_reg(L2_ENTRY5_ADDR, entry[5]); if (ret != E_OK) return ret;

uint32_t ctrlValue = (1U << 31) | (1U << 30) | (1U << 28) | (1U << 27) | (3U << 23);
ret = spi_write_reg(L2_CTRL_ADDR, ctrlValue);
if (ret != E_OK) return ret;

do {
ret = spi_read_reg(L2_CTRL_ADDR, &ctrlReg);
if (ret != E_OK) return ret;
} while (ctrlReg & (1U << 31));

return E_OK;
}

This was the current implementation for Creating a Dynamic Entry can you cross verify with FAE whether this implementation is correct !!
Any other changes need to be done 

[PavelL]

Hello @Atkinson ,

your code looks good. However, if you want to access dynamic tables by SPI, the entry addresses are without FF and shifted right by 2. As I already mentioned in some of my previous post.

So, #define L2_ENTRY0_ADDR 0xFF00008c should be #define L2_ENTRY0_ADDR 0x00000023

But it depends, what your routine spi_write_reg actually does.

Here is output of the write_l2_lookup_table.py , incl. my debug prints (tx/rx refers to data what would be seen on SPI wires by oscilloscope or by logic analyzer):

DBG spi_tx: ['0x02000290', '0xAABBCCDD']
DBG spi_rx: ['0x02000290', '0x00000000']
DBG spi_read 0x0029 -> 0x00000000
DBG spi_write 0x0023 <- 0x37FFFA00
DBG spi_tx: ['0x80000230', '0x37FFFA00']
DBG spi_write 0x0024 <- 0x119A22AB
DBG spi_tx: ['0x80000240', '0x119A22AB']
DBG spi_write 0x0025 <- 0xFF807089
DBG spi_tx: ['0x80000250', '0xFF807089']
DBG spi_write 0x0026 <- 0xFFFFFFFF
DBG spi_tx: ['0x80000260', '0xFFFFFFFF']
DBG spi_write 0x0027 <- 0xF1FFFFFF
DBG spi_tx: ['0x80000270', '0xF1FFFFFF']
DBG spi_write 0x0028 <- 0x1FFE7EFF
DBG spi_tx: ['0x80000280', '0x1FFE7EFF']
DBG spi_write 0x0029 <- 0xD9800000
DBG spi_tx: ['0x80000290', '0xD9800000']
+-------+-------------+-------------------+--------+---------+-------+
| INDEX | DESTPORTS | MACADDR | VLANID | ENFPORT | IOTAG |
+-------+-------------+-------------------+--------+---------+-------+
| 256 | 11111111111 | 11:22:33:44:55:66 | 14 | 1 | 1 |
+-------+-------------+-------------------+--------+---------+-------+
L2 Lookup Table Entry Written (SW1)

Regarding the FAE request, FAE is not on my escalation path. Your company has assigned FAE, so you can contact FAE directly.

Best regards,

Pavel

[Atkinson]

Hi @PavelL 

I am having some certain questions
1.) This Debug print of l2_write_lookup_table.py was taken from SJA1110 EVM Board Implementation ryt its not from S32G-VNP RDB Board? and we can't implement l2_write_lookup_table.py in S32G-VNP-RDB32 Board directly 

2.)can you provide me the code of SPI_read and Spi_write for integrating with the above code?
because in through the implementation in S32G writing it via SPI_Read and SPI_write is doing the operation but unable to see the Dynamic Entry getting added

Std_ReturnType spi_read_reg(uint32_t regAddress, uint32_t* regValue)
{
Std_ReturnType ret;
uint32_t TxChBuf[65] = {0};
uint32_t RxChBuf[65] = {0};
uint16_t regCount = 1;

Siul2_Dio_Ip_WritePin(SPI_MCU_ES1_CS_AP_PORT, SPI_MCU_ES1_CS_AP_PIN, 0U);

ret = getSpiAPCommand(false, regAddress, regCount, TxChBuf, regValue);
if (ret != E_OK) {
Siul2_Dio_Ip_WritePin(SPI_MCU_ES1_CS_AP_PORT, SPI_MCU_ES1_CS_AP_PIN, 1U);
return ret;
}

ret=Spi_SetupEB(5u, (uint8_t*)TxChBuf, (uint8_t*)RxChBuf, 8u);
if (ret == E_OK) {
ret=Spi_SyncTransmit(SpiConf_SpiSequence_SpiSequence_sja);
if (ret == E_OK) {
*regValue = RxChBuf[1];
}
}

Siul2_Dio_Ip_WritePin(SPI_MCU_ES1_CS_AP_PORT, SPI_MCU_ES1_CS_AP_PIN, 1U);
return ret;
}

Std_ReturnType spi_write_reg(uint32_t regAddress, uint32_t regValue)
{
Std_ReturnType ret;
uint32_t TxChBuf[65] = {0};
uint32_t RxChBuf[65] = {0};
uint16_t regCount = 1;
uint32_t regValArray[1] = { regValue };

// Pull chip select LOW
Siul2_Dio_Ip_WritePin(SPI_MCU_ES1_CS_AP_PORT, SPI_MCU_ES1_CS_AP_PIN, 0U);

ret = getSpiAPCommand(true, regAddress, regCount, TxChBuf, regValArray);
if (ret != E_OK) {
Siul2_Dio_Ip_WritePin(SPI_MCU_ES1_CS_AP_PORT, SPI_MCU_ES1_CS_AP_PIN, 1U);
return ret;
}

ret=Spi_SetupEB(5u, (uint8_t*)TxChBuf, (uint8_t*)RxChBuf, 8u);
if (ret == E_OK) {
ret=Spi_SyncTransmit(SpiConf_SpiSequence_SpiSequence_sja);
}

Siul2_Dio_Ip_WritePin(SPI_MCU_ES1_CS_AP_PORT, SPI_MCU_ES1_CS_AP_PIN, 1U);
return ret;
}

Correct me if i am wrong !!

3.)I have changed the Register address to #define L2_ENTRY0_ADDR 0x00000023
but still i am not able to identify the table which i am trying to add getting reflected when i transmit the message 

[PavelL]

Hello @Atkinson ,

1. Yes, the host tools were originally developed for the SJA1110-EVM board. I personally use these scripts with debug prints to verify my understanding of register access. While you cannot run them directly on the S32G-VNP-RDB2 platform, the underlying logic can be adapted, since the S32G accesses the SJA1110 via SPI.

2. If you're looking for SPI read/write implementations for the S32G platform, you have two main options:

• Refer to the SPI examples provided in the S32G RTD 4.0.0 package.
• Alternatively, I recommend posting a dedicated question on the NXP S32G Community Forum, where the S32G support team can assist you further. I focus primarily on Automotive Ethernet topics, with limited overlap into platform-specific drivers.

3. If I understand correctly, you're referring to the L2 Lookup Table described in Table 1182 of UM11107. This table consists of six 32-bit registers per entry. You can see this structure reflected in the debug output from the Python script.

Best regards,

Pavel

[Atkinson]

Hi @PavelL 

3.)I have changed the Register address to #define L2_ENTRY0_ADDR 0x00000023
but still i am not able to identify the table which i am trying to add getting reflected when i transmit the message 
"If I understand correctly, you're referring to the L2 Lookup Table described in Table 1182 of UM11107. This table consists of six 32-bit registers per entry. You can see this structure reflected in the debug output from the Python script."

So i am facing up with the issue in a way where i am trying to write the data into address which need to create a Dynamic Entry in L2 lookup table but its not creating a Dynamic Entry 

#define L2_ENTRY0_ADDR 0x00000023
#define L2_ENTRY1_ADDR 0x00000024
#define L2_ENTRY2_ADDR 0x00000025
#define L2_ENTRY3_ADDR 0x00000026
#define L2_ENTRY4_ADDR 0x00000027
#define L2_ENTRY5_ADDR 0x00000028
#define L2_CTRL_ADDR 0x00000029

#define L2_CTRL_VALID_BIT (1U << 31)
#define L2_CTRL_WR_RDB_BIT (1U << 30)
#define L2_CTRL_VALIDENTRY_BIT (1U << 28)
#define L2_CTRL_HOSTCMD_SHIFT 23
#define L2_CTRL_HOSTCMD_WRITE (0b011U << L2_CTRL_HOSTCMD_SHIFT)

Std_ReturnType CreateL2Entry(uint32_t entry[6])
{
uint16_t INDEX = 11;
uint64_t MACADDR = 0x661122334455;
uint64_t MACADDR_MASK = 0xFFFFFFFFFFFF;
uint16_t VLANID = 3;
uint16_t VLANID_MASK = 0xFFF;
uint8_t IOTAG = 0;
uint8_t IOTAG_MASK = 0;
uint8_t SRCPORT = 5;
uint8_t SRCPORT_MASK = 0xF;
uint8_t DESTPORTS = 0x02;
uint8_t ENFPORT = 1;
uint8_t RETAG = 0;
uint8_t MIRROR = 0;
uint8_t TAKETS = 0;
uint16_t MIRR_VLAN = 0xFFF;
uint8_t TRAPTOHOST = 0;
uint8_t CBSIDIN = 0x3F;
uint8_t CBENONDA = 0;
uint16_t VLIDX = 0xFFF;
uint8_t SA_POLICE = 0;
uint8_t DA_POLICE = 0;

entry[0] = ((INDEX & 0x03FF) << 1) |
((ENFPORT & 0x1) << 11) |
((DESTPORTS & 0x7FF) << 12) |
((SRCPORT & 0xF) << 23) |
((MACADDR & 0x1F) << 27);

entry[1] = (uint32_t)((MACADDR >> 5) & 0xFFFFFFFF);

entry[2] = (((MACADDR >> 37) & 0x7FF) << 0) |
((VLANID & 0xFFF) << 11) |
((IOTAG & 0x1) << 23) |
((MACADDR_MASK & 0xFF) << 24);

entry[3] = (uint32_t)((MACADDR_MASK >> & 0xFFFFFFFF);

entry[4] = (((MACADDR_MASK >> 40) & 0xFF) << 0) |
((VLANID_MASK & 0xFFF) << |
((IOTAG_MASK & 0x1) << 20) |
((SRCPORT_MASK & 0xF) << 21) |
((RETAG & 0x1) << 25) |
((MIRROR & 0x1) << 26) |
((TAKETS & 0x1) << 27) |
((MIRR_VLAN & 0xF) << 28);

entry[5] = (((MIRR_VLAN >> 4) & 0xFF) << 0) |
((TRAPTOHOST & 0x1) << |
((CBSIDIN & 0x3F) << 9) |
((CBENONDA & 0x1) << 15) |
((VLIDX & 0xFFF) << 17) |
((SA_POLICE & 0x1) << 29) |
((DA_POLICE & 0x1) << 30);

return E_OK;
}

Std_ReturnType WriteL2LookupEntry(uint8_t swt)
{
if (swt > 0) return E_NOT_OK;

Std_ReturnType ret;
uint32_t ctrlReg = 0;
uint32_t entry[6];

// Step 1: Create the entry
ret = CreateL2Entry(entry);
if (ret != E_OK) return ret;

// Step 2: Wait for VALID bit to clear
do {
ret = spi_read_reg(L2_CTRL_ADDR, &ctrlReg);
if (ret != E_OK) return ret;
} while (ctrlReg & L2_CTRL_VALID_BIT);

// Step 3: Write entry data to registers
ret = spi_write_reg(L2_ENTRY0_ADDR, entry[0]); if (ret != E_OK) return ret;
ret = spi_write_reg(L2_ENTRY1_ADDR, entry[1]); if (ret != E_OK) return ret;
ret = spi_write_reg(L2_ENTRY2_ADDR, entry[2]); if (ret != E_OK) return ret;
ret = spi_write_reg(L2_ENTRY3_ADDR, entry[3]); if (ret != E_OK) return ret;
ret = spi_write_reg(L2_ENTRY4_ADDR, entry[4]); if (ret != E_OK) return ret;
ret = spi_write_reg(L2_ENTRY5_ADDR, entry[5]); if (ret != E_OK) return ret;

// Step 4: Set control register to trigger write

uint32_t ctrlValue = (1U << 31) |
(1U << 30) |
(1U << 28) |
(1U << 27) |
(3U << 23);

ret = spi_write_reg(L2_CTRL_ADDR, ctrlValue);
if (ret != E_OK) return ret;

do {
ret = spi_read_reg(L2_CTRL_ADDR, &ctrlReg);
if (ret != E_OK) return ret;
} while (ctrlReg & L2_CTRL_VALID_BIT);

return E_OK;
}


can you check once whether any issues is there because its not creating Dynamic Entry for the L2 lookup Table ?

[PavelL]

Hello @Atkinson ,

1. Bit Shift Syntax (<<, >>)
It appears that some of the bit shift operators in your code were replaced with HTML entities like &lt;&lt; and &gt;&gt;. This typically happens when code is copied into web-based platforms. Anyway, please check it directly in your code.

#define L2_CTRL_VALID_BIT (1U &lt;&lt; 31)

should be:
#define L2_CTRL_VALID_BIT (1U << 31)

2. Entry Issue
There are several syntax errors and missing shift values in the CreateL2Entry() function, particularly in entry[3], entry[4], and entry[5]. These may result in incomplete or invalid register writes. 

e.g. 

((TRAPTOHOST & 0x1) << |

I recommend comparing your implementation against the Python reference script, which correctly constructs all six 32-bit words of the L2 entry.

Best regards,

Pavel

[Atkinson]

Hi @PavelL 

int WriteL2LookupEntry(int cs)
{
const uint32_t DESTPORTS = 0x002;
const uint32_t INDEX = 8;
const uint64_t MACADDR = 0x661122334455;
const uint64_t MACADDR_MASK = 0xffffffffffff;
const uint32_t VLANID = 0;
const uint32_t VLANID_MASK = 0xfff;
const uint32_t IOTAG = 0;
const uint32_t IOTAG_MASK = 0;
const uint32_t SRCPORT = 0x5;
const uint32_t SRCPORT_MASK = 0xF;
const uint32_t ENFPORT = 0;
const uint32_t RETAG = 0;
const uint32_t MIRROR = 0;
const uint32_t TAKETS = 0;
const uint32_t MIRR_VLAN = 0xFFF;
const uint32_t TRAPTOHOST = 0;
const uint32_t CBSIDIN = 0x3F;
const uint32_t CBENONDA = 0;
const uint32_t VLIDX = 0xFFF;
const uint32_t SA_POLICE = 0;
const uint32_t DA_POLICE = 0;

uint32_t L2_OFFSET = 0x23;
uint32_t L2CTRL_OFFSET = 0x29;
const uint32_t SWREG_BASE = 0x00000000;

const uint32_t VALID = 1U;
const uint32_t RDWRSET = 1U;
const uint32_t VALIDENT = 1U;
const uint32_t HOSTCMD = 3U;
const uint32_t MGMTROUTE = 0U;
const uint32_t LOCKED = 1U;
const uint32_t ERROR = 0U;

uint32_t L2_ADDRESS = SWREG_BASE + L2_OFFSET;
uint32_t L2_ADDRESS_CTL = SWREG_BASE + L2CTRL_OFFSET;

uint32_t l2Entry[ADDRESS_RANGE] = {0};

l2Entry[0] = ((INDEX & 0x03FF) << 1)
| ((ENFPORT & 0x1) << 11)
| ((DESTPORTS & 0x7FF) << 12)
| ((SRCPORT & 0xF) << 23)
| ((uint32_t)(MACADDR & 0x1F) << 27);

l2Entry[1] = (uint32_t)((MACADDR >> 5) & 0xFFFFFFFF);

l2Entry[2] = (uint32_t)(((MACADDR >> 37) & 0x7FF) << 0)
| ((VLANID & 0xFFF) << 11)
| ((IOTAG & 0x1) << 23)
| ((uint32_t)(MACADDR_MASK & 0xFF) << 24);

l2Entry[3] = (uint32_t)((MACADDR_MASK >> & 0xFFFFFFFF);

l2Entry[4] = ((uint32_t)((MACADDR_MASK >> 40) & 0xFF) << 0)
| ((VLANID_MASK & 0xFFF) <<
| ((IOTAG_MASK & 0x1) << 20)
| ((SRCPORT_MASK & 0xF) << 21)
| ((RETAG & 0x1) << 25)
| ((MIRROR & 0x1) << 26)
| ((TAKETS & 0x1) << 27)
| ((MIRR_VLAN & 0xF) << 28);

l2Entry[5] = (((MIRR_VLAN >> 4) & 0xFF) << 0)
| ((TRAPTOHOST & 0x1) <<
| ((CBSIDIN & 0x3F) << 9)
| ((CBENONDA & 0x1) << 15)
| ((VLIDX & 0xFFF) << 17)
| ((SA_POLICE & 0x1) << 29)
| ((DA_POLICE & 0x1) << 30);
uint32_t status = 0;
do {
Std_ReturnType ret = spi_read_reg(L2_ADDRESS_CTL, &status);
if (ret != E_OK) {
return -1;
}
} while ((status >> VALID_BIT_SHIFT) & 1U);

for (int i = 0; i < ADDRESS_RANGE; i++) {
Std_ReturnType ret = spi_write_reg(L2_ADDRESS + i, l2Entry[i]);
if (ret != E_OK) {
return -2;
}

uint32_t readBack = 0;
ret = spi_read_reg(L2_ADDRESS + i, &readBack);
if (ret != E_OK || readBack != l2Entry[i]) {
return -3;
}
}

uint32_t controlL2Entry = 0;
controlL2Entry |= (VALID << VALID_BIT_SHIFT);
controlL2Entry |= (RDWRSET << RDWRSET_BIT_SHIFT);
controlL2Entry |= (ERROR << ERROR_BIT_SHIFT);
controlL2Entry |= (LOCKED << LOCKED_BIT_SHIFT);
controlL2Entry |= (VALIDENT << VALIDENT_BIT_SHIFT);
controlL2Entry |= (MGMTROUTE << MGMTROUTE_BIT_SHIFT);
controlL2Entry |= (HOSTCMD << HOSTCMD_BIT_SHIFT);

Std_ReturnType ret = spi_write_reg(L2_ADDRESS_CTL, controlL2Entry);
if (ret != E_OK) {
return -4;
}

do {
ret = spi_read_reg(L2_ADDRESS_CTL, &status);
if (ret != E_OK) {
return -5;
}
} while ((status >> VALID_BIT_SHIFT) & 1U);

return 0;
}

This is my revised code implementation 
can you verify once this implementation will bring a Dynamic Entry. so i tried debugging it by readingback the register value whether the values are getting written into the register i could able to see the values are written into the register but i am not sure whether the enrty is created or not ?
and also the reflection of Dynamic entry of L2 lookup table is not getting reflected ?
so how can i verify the L2 lookup table enrty is created ?

[PavelL]

Hello @Atkinson ,

There are missing shift values and incomplete expressions in entry[3], entry[4], and entry[5]. These may result in incorrect register values. I recommend comparing your logic against the Python reference script, which constructs the L2 entry correctly.

After writing, try sending a frame that matches the MAC/VLAN/port criteria of the entry and observe whether it is forwarded according to the DESTPORTS field.

Best regards,

Pavel

[Atkinson]

Hi @PavelL 

int WriteL2LookupEntry(int cs)
{
const uint32_t DESTPORTS = 0x004;
const uint32_t INDEX = 2;
const uint64_t MACADDR = 0x112233445566;
const uint64_t MACADDR_MASK = 0xffffffffffff;
const uint32_t VLANID = 0;
const uint32_t VLANID_MASK = 0x0;
const uint32_t IOTAG = 0;
const uint32_t IOTAG_MASK = 0;
const uint32_t SRCPORT = 0x6;
const uint32_t SRCPORT_MASK = 0xF;
const uint32_t ENFPORT = 0;
const uint32_t RETAG = 0;
const uint32_t MIRROR = 0;
const uint32_t TAKETS = 0;
const uint32_t MIRR_VLAN = 0xFFF;
const uint32_t TRAPTOHOST = 0;
const uint32_t CBSIDIN = 0x3F;
const uint32_t CBENONDA = 0;
const uint32_t VLIDX = 0xFFF;
const uint32_t SA_POLICE = 0;
const uint32_t DA_POLICE = 0;

uint32_t L2_OFFSET = 0x23;
uint32_t L2CTRL_OFFSET = 0x29;
const uint32_t SWREG_BASE = 0x00000000;

const uint32_t VALID = 1U;
const uint32_t RDWRSET = 1U;
const uint32_t VALIDENT = 1U;
const uint32_t HOSTCMD = 3U;
const uint32_t MGMTROUTE = 0U;
const uint32_t LOCKED = 1U;
const uint32_t ERROR = 0U;

uint32_t L2_ADDRESS = SWREG_BASE + L2_OFFSET;
uint32_t L2_ADDRESS_CTL = SWREG_BASE + L2CTRL_OFFSET;

uint32_t l2Entry[ADDRESS_RANGE] = {0};

l2Entry[0] = (((INDEX & 0x03ff) << (1 % 32)) + ((ENFPORT & 1) << (11 % 32))
+ ((DESTPORTS & 0x7FF) << (12 % 32)) + ((SRCPORT & 0xF) << (23 % 32))
+ ((MACADDR & 0x1F) << (27 % 32)));

l2Entry[1] = (((MACADDR >> 5) & 0xFFFFFFFF));

l2Entry[2] = ((((MACADDR >> 37) & 0x7FF) << (64 % 32)) + ((VLANID & 0xFFF) << (75 % 32))
+ ((IOTAG & 1) << (87 % 32)) + ((MACADDR_MASK & 0xFF) << (88 % 32)));

l2Entry[3] = (((MACADDR_MASK >> & 0xFFFFFFFF));

l2Entry[4] = (((MACADDR_MASK >> 40) & 0xFF << (128 % 32)) + ((VLANID_MASK & 0xfff) << (136 % 32))
+ ((IOTAG_MASK & 1) << (148 % 32)) + ((SRCPORT_MASK & 0xF) << (149 % 32))
+ ((RETAG & 0x1) << (153 % 32)) + ((MIRROR & 0x1) << (154 % 32))
+ ((TAKETS & 0x1) << (155 % 32)) + ((MIRR_VLAN & 0xF) << (156 % 32)));

l2Entry[5] = (((MIRR_VLAN >> 4) & 0xFF << (160 % 32)) + ((TRAPTOHOST & 0x1) << (168 % 32))
+ ((CBSIDIN & 0x3F) << (169 % 32)) + ((CBENONDA & 0x1) << (175 % 32))
+ ((VLIDX & 0xFFF) << (177 % 32)) + ((SA_POLICE & 0x1) << (189 % 32))
+ ((DA_POLICE & 0x1) << (190 % 32)));
uint32_t status = 0;
do {
Std_ReturnType ret = spi_read_reg(L2_ADDRESS_CTL, &status);
if (ret != E_OK) {
return -1;
}
} while ((status >> VALID_BIT_SHIFT) & 1U);

for (int i = 0; i < ADDRESS_RANGE; i++) {
Std_ReturnType ret = spi_write_reg(L2_ADDRESS + i, l2Entry[i]);
if (ret != E_OK) {
return -2;
}

uint32_t readBack = 0;
ret = spi_read_reg(L2_ADDRESS + i, &readBack);
if (ret != E_OK || readBack != l2Entry[i]) {
return -3;
}
}

uint32_t controlL2Entry = 0;
controlL2Entry = ((VALID << 31) + (RDWRSET << 30) + (ERROR << 29) + (LOCKED << 28) + (VALIDENT << 27) +
(MGMTROUTE << 26) + (HOSTCMD << 23));

Std_ReturnType ret = spi_write_reg(L2_ADDRESS_CTL, controlL2Entry);
if (ret != E_OK) {
return -4;
}

do {
ret = spi_read_reg(L2_ADDRESS_CTL, &status);
if (ret != E_OK) {
return -5;
}
} while ((status >> VALID_BIT_SHIFT) & 1U);

return 0;
}

I have changed the implementation similar to Python script. if you found any errors can you send me the changes please

Python script

        # Write Control

        platform.spi_write(L2_ADDRESS_CTL, controlL2Entry, cs)

        table = prettytable.PrettyTable(

            ("INDEX", "DESTPORTS", "MACADDR", "VLANID", "ENFPORT", "IOTAG"))

        entry = (

            str(INDEX), '{0:11b}'.format(DESTPORTS), mac_to_str(MACADDR), str(VLANID),

            str(ENFPORT), str(IOTAG))

        table.add_row(entry)

        print(table.get_string())

"After writing, try sending a frame that matches the MAC/VLAN/port criteria of the entry and observe whether it is forwarded according to the DESTPORTS field"
I am trying to send in this way as you mentioned but this reflection is not seen 
I am unable to see my entry is getting reflected ?
is there any other things need to be setted up ??

In Python script after writing the register value for controll2entry into L2_ADDRESS_CTL
there were few lines of code which does adding a entry into "prettytable"

Do we need to this also same and whether we have provision to do this ??

 

[PavelL]

Hello @Atkinson ,

In your code, there are missing shift values in entry[3], and missing or misplaced brackets in entry[3], entry[4], and entry[5].

To verify your L2 lookup configuration, you may consider setting the entry as a static one instead of dynamic — this can help isolate whether the issue is with the entry format or the dynamic update mechanism.

Also, please note that the "pretty tables" in the Python script are used only for formatting output in the command window — they do not affect the functionality or register configuration.

Best regards,

Pavel

[Atkinson]

Hi @PavelL 

"In your code, there are missing shift values in entry[3], and missing or misplaced brackets in entry[3], entry[4], and entry[5]."
I have implemented it as same as the python code sorry i am nots sure where i am missing the brackets and shift values. can you kindly provide me the aligned code which might be more clear sorry for missing out the brackets and shift
It would be more helpful and clear if you provide me the exact entry[3],entry[4], entry[5]