Creation of DCD and IVT image for S32G3XX

[Ganesh_Pawar]

Hi NXP Team,

  Here is a query observed in RDB3 board related to QSPI boot from M7 core. The explanation is as follows. 

    In S32G-VNP-RDB3 board ,RTD version 4.0.0 using Uart example , Uart1 is used connected to J1 for M7 core , In debug mode the uart logs are observed using S32 Debug Probe.

 As per the resources provided by NXP for generation of IVT binary for S32G2XX,

we have followed the same procedure for generating the IVT image for S32G3xx. 

boot selection from M7 core , Boot media from QSPI are some of the selection done while generating IVT.

After flashing it using Flash Tool ,

a) M7 uart logs are not observed  .

Is there any document for creating the IVT and DCD image generation for S32G3xx ,

 We would request you to provide some inputs on this issue. 

Thanks and regards,

Ganesh Pawar

[Ganesh_Pawar]

Hi Daniel,

               Thanks for the reply..!!!

The plan is to boot the IVT image from QSPI , as per the presentation document the boot is selected as SD card , is there any document for QSPI boot need to know the SRAM address to be set in the linker file. Please provide reference

"Which resources have you used? For creating and IVT under S32G3/RDB3 platform"

Please attach the respective document to refer to generate the DCD for S32G3/RDB3 platform

"As of using the UART example following the SW enablement guide steps, we understand that there is a conflict with the D-CACHE enablement. You should be able to delete the following preprocessor define"

With this changes , there was no issue found in debug mode but while creating DCD it was throwing error " file contains error cannot export " .

Requesting to provide inputs on these queries as soon as possible.

Thanks and regards,

Ganesh Pawar

[Daniel-Aguirre · Accepted solution]

Hi,

Thanks for your feedback. The same SW enablement guide can be used for IVT generation using the QSPI interface, the only difference will be to select the QSPI to be the boot interface rather than the uSDHC one. On regards of the S32 Flash Tool, the algorithm should be the one related to your NOR Flash. Under RDB3, the algorithm should be the following:

As for an specific document, there might not be any available, but we could recommend looking into the AN13750 available under the S32G2 product page (link: S32G2 Safe and Secure Vehicle Network Processor | NXP Semiconductors) in which an IVT for QSPI and QSPI parameters is shown.

Again, the SW enablement guide should provide the required information for both QSPI and SD boot interface.

As for the DCD, this seems related to a different problem, directly related to the DCD itself. We don't see any instructions on creating a DCD under the SW enablement guide for RDB3, you should be able to put the section on reserved as told under the guide.

Please, let us know.

[Ganesh_Pawar]

Hi Daniel,
Thanks for your support on this much appreciated, boot from QSPI is done as per the procedure mentioned in the SW enablement guide.

[Daniel-Aguirre]

Hi,

Can you help us elaborate more on the following comment?:

"As per the resources provided by NXP for generation of IVT binary for S32G2XX,"

Which resources have you used? For creating and IVT under S32G3/RDB3 platform, we recommend looking into the SW Enablement Guide available under the RDB3 product page (link: S32G3 Vehicle Networking Reference Design | NXP Semiconductors).

As of using the UART example following the SW enablement guide steps, we understand that there is a conflict with the D-CACHE enablement. You should be able to delete the following preprocessor define:

And see the expected outcome under your terminal. We can see it from our side after this modification.

Please, let us know.