Cache coherency for S32G274ardb2

[k_kikuchi]

Hello,

We are verifying that cache coherency is maintained across Cortex-A53 clusters.

The U-Boot bootloader for S32G_BSP30.0 is built with s32g274ardb2_defconfig (no source modification).
ATF is not used. The global enable bit in the XRDC control register (XRDC_CR) is 0.

In this combination, is the cache coherency between Cortex-A53 Cluster0 and Cortex-A53 Cluster1 maintained when the OS is booted from the U-Boot ?
If not, what settings should be made to maintain cache coherency between clusters?
Below are the register values for XRDC_CR and NCORE (only those with valid bits set).

<env>
board: s32g-vnp-rdb2
bootloader: u-boot of S32G_BSP30.0 (ATF not used)
core: CA53 x 4core use
OS:my customer's RTOS

<reg dump after init_core() executed>

[registers address : value]

XRDC Control (CR) register
XRDC0_CR 401a4000: 0000008a
XRDC1_CR 44004000: 0000008a

Coherent Agent Interface Unit registers
CAIU0_CAIUTC 50400000: 00000001
CAIU0_CAIUTA 50400004: 00000001
CAIU0_CAIUID 50400ffc: 00008001
CAIU1_CAIUTC 50401000: 00000001
CAIU1_CAIUID 50401ffc: 00008101

Non-coherent bridge unit (NCBU) register
NCBU0_NCBUTC 50460000: 00000001
NCBU0_NCBUID 50460ffc: 00030001
NCBU1_NCBUTC 50461000: 00000001
NCBU1_NCBUID 50461ffc: 00030101

Directory unit (DIRU) register
DIRU_DIRUSFE 50480010: 00000001
DIRU_DIRUCASE0 50480040: 00000003
DIRU_DIRUID 50480ffc: 00000001

Coherent memory interface unit (CMIU) register
CMIU_CMIUID 504c0ffc: 00000001

Coherent subsystem (CSR) register
CSR_CSADSE0 504ff040: 00000003
CSR_CSSFIDR0 504fff00: 0cb007ff
CSR_CSUID 504ffff8: 01010202
CSR_CSID 504ffffc: 00000109

CCTI fault controller register
CCTI_COREID 50500000: 7073b716
CCTI_REVISIONID 50500004: c67f8700
CCTI_BIST_DONE 50500038: 00000002
CCTI_BIST_TO1 5050003c: 0000ffff
CCTI_BIST_TO2 50500040: 000000ff

Functional safety controller (FSC) register
FSC_SCCETH 50600008: 00000001

[Daniel-Aguirre]

Hi,

For our understanding, Cache coherency should be done through the Snoop Control Unit (provided from ARM).

Still, between both clusters, there is no clear information.

Let us see if there is something we could share that helps with this topic.

We thank you for your patience.

[Daniel-Aguirre]

Hi,

We have received the following information:

"Yes, the cache coherency between clusters is maintained by NCORE. It is a CCI-400-like module, and is configured in U-BOOT within BSP 30."

Please, let us know if this information was helpful or not.

[k_kikuchi]

Thanks for your response.

Let me check the register values after a module like CCI-400 is configured in the U-Boot.
After executing the Init_core() function, I checked the value of Coherent Agent Interface Unit registers.

[registers address : value]
CAIU0_CAIUTC 50400000: 00000001
CAIU0_CAIUTA 50400004: 00000001
CAIU1_CAIUTC 50401000: 00000001
CAIU1_CAIUTA 50401004: 00000000

From these results, we infer that each cluster is in the following states

Cluster0: Agent Transaction Enable / Transaction Active
Cluster1: Agent Transaction Enable / Transaction Inactive

Which of the following is a valid bit in the CAIUTA register?

1. Always as long as cache coherency is maintained.
2. only while cache transfers are occurring to maintain cache coherency.
3. when other special conditions are met.

[Daniel-Aguirre]

Hi,

Could you elaborate more on the "Which of the following is a valid bit in the CAIUTA register?", we understand that you are asking which bits are valid ones on the register. If so, the following information on the reference manual should provide this:

CAIU Transaction Activity (CAIUTA) [Chapter 7.10.1.1.2, Page 131, S32G2 Reference Manual, Rev. 6, 11/2022]:

Please, let us know if this information was helpful or not.

[k_kikuchi]

Thanks for your response.

I would like to clarify "the unit is performing any activity related to the native agent coherenttransactions" in the manual.
When is each bit in the CAIUTA register turned on?

A. Only while performing coherence preserving operations.
B. Only while coherence is maintained (0 if cache mismatch)
C. Always 1 if Agent Transaction is Enable

The following is a timing chart based on the interpretation of each of A, B, and C.
The chart starts with a cache mismatch, and the cache is matched at the timing of "Maintaining Cache Coherency".

[Daniel-Aguirre]

Hi,

Thanks for the feedback.

As said in the reference manual (and you are saying) [Page 131, S32G2 Reference Manual, Rev. 6, 11/2022]:

"Ncore writes a 1 to this field when the unit is performing any activity related to ... and is cleared otherwise."

As implied in the RM, it should only be set if Ncore is executing the related activity, not related to a system state.

We could also recommend looking into the "AN12887 - S32G2 Data Cache Coherency" available under the S32G2 product site (link: S32G2 Safe and Secure Vehicle Network Processor | NXP Semiconductors).

Please, let us know.