Hello everybody,
I'm testing the PWM using EMIOS and I facing some doubts:
Informations:
CLK is 160MHz.
S32K344uC and S32K3 RTD AUTOSAR 4.4 2.0.1 D2207 package.
1) I calculated the period this way:
period[ticks] = CLK_PWM / PERIOD_FREQ
16000 = 160MHz / 10KHz
So, I put the "16000" in the option "period" on "Emios_Mcl_Ip_SetCounterBusPeriod" and in the MCU tool in the options of channel (Emios_Pwm) and (Emios_Mcl_Ip).
Emios_Pwm:
Emios_Mcl_Ip:
But the result is 5KHz:
When I put "8000" instead "16000", the result is 10KHz... Why? the calculation isn't it (CORE_CLK/global prescaler/internal prescaler)?
I used this prescalers:
2) About the duty cycle, it look like the same problem as commented above, if I choose for example "8000" as period and I defined the channel with "8000" of duty cycle, the duty cycle output is 50% and not 100%¨. Why? The calculation isn't it (dutycycle (%) * period [ticks] / 100)?
I'm using this function to define the dutycycle: "Emios_Pwm_Ip_SetDutyCycle"
3) And about the 100% of duty cycle, as we can see this comment about this function:
When I choose any period and I set duty cycle value grater period value, the result is 0% and not 100% (Of course, the value is not more than 16 bits of the counter register, I tested it with, for example: period=8000 and dutycycle>=8000).
The 100% of duty cycle just work when I set for example 7998 in this example above.
Thanks very much,
MVR
Solved! Go to Solution.
Hi @MVR
By setting the mode to UP_DOWN_COUNTER you are doing a double count of ticks per period, what I mean is that when the signal goes up in this case it will count 8K ticks and when it goes down it will do another 8K tick count giving us a total of 16K ticks , resulting in a PWM signal frequency of 10KHz.
Regarding the duty cycle, you can see in the Emios_Pwm_Ip_SetDutyCycleOpwmcb function that it checks if the Duty Cycle is 0 or equal to (ChPeriod * 2U) - 2U) or if it is none of the above. This gives us to understand that to have a Duty Cycle of 100%, you have to send twice the period minus two, that's why when you send a value of 7999 in Emios_Pwm_Ip_SetDutyCycle, what you get is a Duty Cycle of 50% and when giving a value of 15998 the Duty Cycle is 100%.
NOTE:
PWM frequency = CORE_CLK / global prescaler / internal prescaler / (period [ticks] x 2)
Period[ticks] = CORE_CLK / PERIOD_FREQ / 2
B.R.
VaneB
what is the differnt betwen defult period on MCL and the period on emios ?
Hi @MVR
As you know eMIOS is clocked by CORE_CLK. eMIOS divides its clock by the global prescaler (MCR[GPRE] + 1) and routes the resulting prescaled clock output to the channel internal prescaler (Cn[UCPRE] + 1). Thus channel internal counter counts (CORE_CLK/global prescaler/internal prescaler) clock.
For example if the channel is running in OPWFMB mode, its PWM frequency is calculated as:
PWM frequency = CORE_CLK / global prescaler / internal prescaler / (B1+1)
Where B1 is the value of the B register.
I hope this will help you.
B.R.
VaneB
PWM frequency = CORE_CLK / global prescaler / internal prescaler / (B1+1)?
Can we use this formuler for the OPWMB mode too?
Hi @VaneB
Ok, but if I put the values into the calculation, is exactly what I said:
PWM frequency = CORE_CLK / global prescaler / internal prescaler / (B1+1)
PWM frequency = 160MHz / 1 / 1 / (16000+1)
PWM frequency ~= 10KHz
What did I do wrong in this calculation, seeing my previously submitted configuration? If this is right, why can't we see 10KHz in the end result like shown above?
Thanks.
Hi @MVR
Your problem seems to be in the configuration of the Master Bus Mode Type in Emios_Mcl_Ip, when defining the mode in UP_DOWN_COUNTER when defining the mode in UP_DOWN_COUNTER the frequency is divided by two, I recommend defining it as UP_COUNTER OR DOWN_COUNTER.
If this does not solve the problem, attach your code so I can review it.
B.R.
VaneB
Hello @VaneB ,
So, I need to use UP_DOWN_COUNTER because I need a trigger at the beginning of period to ADC conversion. With UP_COUNTER or DOWN_COUNTER it doesn't work, right?
Follow my code with the setup of PWM period, PWM duty cycle and even the ADC conversion being triggered at the beginning of period.
I prepared the code for we discuss the problem itself, in PWM.c file we can see:
Where my first point is the first row (about period) - As you said, the clock is divided per 2 because we use UP_DOWN_COUNTER, so I already corrected it, why is it divided per 2? Second point is the second row (duty cycle as half value). And third point are the next 3 rows (100% of duty cycle is not according of function).
Note: I have tested this problem in the board on Friday with another code, now I'm without the board, I will get it tomorrow. So this code I prepared today for we discuss, I have 99% of sure that this will occur as I raised earlier, but I will have 100% of sure only tomorrow when I tested this code in attached.
Thanks.
Hello @VaneB ,
I have tested my code today, and works according I said earlier. And I collected more information as well:
1) About the period, continue the same doubt, why the clock is divided per 2 when we use UP_DOWN_COUNTER? I can't find this information on reference manual.
2) If I defined the period as 8000, why when I set the duty cycle as 8000 the result is 50% and not 100%?
3) The function "Emios_Pwm_Ip_SetDutyCycle" description doesn't match with the implementation:
With my code sent earlier, you can test everything that I said.
Thanks!
MVR
Hi @MVR
By setting the mode to UP_DOWN_COUNTER you are doing a double count of ticks per period, what I mean is that when the signal goes up in this case it will count 8K ticks and when it goes down it will do another 8K tick count giving us a total of 16K ticks , resulting in a PWM signal frequency of 10KHz.
Regarding the duty cycle, you can see in the Emios_Pwm_Ip_SetDutyCycleOpwmcb function that it checks if the Duty Cycle is 0 or equal to (ChPeriod * 2U) - 2U) or if it is none of the above. This gives us to understand that to have a Duty Cycle of 100%, you have to send twice the period minus two, that's why when you send a value of 7999 in Emios_Pwm_Ip_SetDutyCycle, what you get is a Duty Cycle of 50% and when giving a value of 15998 the Duty Cycle is 100%.
NOTE:
PWM frequency = CORE_CLK / global prescaler / internal prescaler / (period [ticks] x 2)
Period[ticks] = CORE_CLK / PERIOD_FREQ / 2
B.R.
VaneB
is it true that the Emios divide the core clock by 2 ?what about flexio _pwm period(ticks) formuler ?
are those formular applies too for OPWMB mode too ? if no
what is the formule?
Great, I understand!!
And yes, I saw into "Emios_Pwm_Ip_SetDutyCycleOpwmcb" as I sent the print. I understood everything but if other people will work with it, will be confused because the description say one thing and the implementation say other thing, like I sent earlier...
But I understood! Thanks my friend have a nice weekend.