Problem with Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat os S32K312

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Problem with Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat os S32K312

Jump to solution
623 Views
jacopo_costella
Contributor II

Hello,

with S32DS Ver. 3.4, after running pin and clock configuration of  S32K312, I tested a simple program and when entering the function:

Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat (file Clock_Ip_DividerTrigger.c)

the debug session crashed ehwn executing the instruction

DividerStatus = Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_MASK;

 

Instance = 0;

SelectorIndex = 0.

Do you have any idea?

 

Thank you very much,

Jacopo

 

 

 

0 Kudos
1 Solution
590 Views
jacopo_costella
Contributor II

Hello Daniel,

thank you very much for your fast feedback. I noticed your suyggestion here;

https://community.nxp.com/t5/S32K/How-to-compile-S32K3-HSE-FW-in-project/m-p/1541925#M18475https://c...

 

which demo were you referring to?

Regards,

Jacopo

 

 

 

 

 

 

 

View solution in original post

0 Kudos
8 Replies
571 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hi @jacopo_costella,

Currently, we have some issues with our system, and the demo can't be located at nxp.com.

We are working on it.

All the HSE_FW documentation can be found in the Secure files under an NDA on the S32K3xx webpage though:

https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-gener...

I understand the HSE_FW hasn't been installed on the MCU yet.

Can you share the project so that I can test it?

 

Thank you,

BR, Daniel

 

 

0 Kudos
564 Views
jacopo_costella
Contributor II

Hello Daniel,

 

thank you for your reply.

 

Please find attached the project.

 

Have a nice day,

 

Jacopo

0 Kudos
558 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hi Jacopo,

I don't have this old RTD version installed, so I can't modify and recompile the project.

Anyway, the clock configuration is not correct.

Please set all the clock as per the RM, Table 148. Option B - Reduced Speed mode (CORE_CLK @ 120 MHz).

This is just an example from Clocking use case examples (RM, Section 24.7.2).
However, any clock frequency selected must adhere to the same clock divider ratios shown in Clocking use case examples.

Otherwise, we can't guarantee the specified functionality of the MCU.

 

Regards,

Daniel

 

 

0 Kudos
523 Views
jacopo_costella
Contributor II

Hello Daniel,

How did you check the incorrect core clock value? From the tool it is set to 120 MHz. 

Regards,

Jacopo

0 Kudos
520 Views
danielmartynek
NXP TechSupport
NXP TechSupport

All the clocks must be set according to the table (including the PLL clock), or at least the ratios between the clocks must be maintained.

 

Regards,

Daniel

0 Kudos
511 Views
jacopo_costella
Contributor II

Hello Daniel,

problem fixed. Thank you very much,

Jacopo

 

0 Kudos
594 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hi @jacopo_costella,

Is the HSE_FW installed?

 

Thanks,

BR, Daniel

0 Kudos
591 Views
jacopo_costella
Contributor II

Hello Daniel,

thank you very much for your fast feedback. I noticed your suyggestion here;

https://community.nxp.com/t5/S32K/How-to-compile-S32K3-HSE-FW-in-project/m-p/1541925#M18475https://c...

 

which demo were you referring to?

Regards,

Jacopo

 

 

 

 

 

 

 

0 Kudos