vddpll

[Fast]

How much current can be safely drawn from VDDPLL on S12X ?

[danielmartynek]

Hi Richard,

This is not specified, but the domain is only for the OSC circuitry, so the load is not significant.

Regards,

Daniel

[Fast]

Do I read it as; VDDPLL is a low load less than 20mA, I can draw say 10mA and not load the internal LDO regulator?

[danielmartynek]

Hi,

Can you specify the MCU?

Thank you,

Daniel

[Fast]

Hi Daniel

9S12XEP100, I did some tests at 75degC

Load resistor                                                                        VDDPLL

100k	1.86
10k	1.86
1k	1.85
100R	1.82
60R	1.80
50R	1.79
40R	1.77

Suggesting for a sample of 1, 10mA is not a problem.

Thank you for your assistance

Rich

[danielmartynek]

Hi Richard,

The thing is it wasn't designed for such a use case.

If you take a look at Section 23.2.5 VDDPLL, VSSPLL — Regulator Output3 (PLL) Pins (S12XEP RM, rev.1,25), 

it states: 

"Signals VDDPLL/VSSPLL are the secondary outputs of VREG_3V3 that provide the power supply for the PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R ceramic)."

So that's the purpose of the pins, to allow connecting the decoupling capacitors.

Regards,

Daniel