not able to update SPI0DR

[kelimagna]

I am using SPI0 on S12ZVLA128. I tried to do send and receive in polling mode. the SPI is in slave mode. I am checking the SPI0SR register every 10ms. The issue is the SPTEF never set, although I can see there is data on the MISO line. Since the SPTEF never set, I cannot update the SPI0DR. The MISO is sending what ever received on MOSI.

Are you able to help? thanks, Ke 

[RadekS]

Hi Ke,

I am not sure what it a root cause in your case. But I have a few points for you.

1. From my point of view, there might be a problem with chip-select (slave select) pin. Is chip-select signal between master and slave used or SS pin is connected to GND at the slave side? Be aware that CPHA=0 mode (data sampling at first SCK edge) is not compatible with static slave select pin … The transfer ends by the rising edge at SS pin. Please check correct CPHA bit settings – must be the same as on the master side. Please check also MODFEN and SSOE bits – they should be both log.1 for active slave select input pin.
2. The S12ZVL has only one SPI0 routing option. The SPI0 signals are routed at pins PS0~PS3. However, these pins may be occupied also by higher priority signals like ECLK, Timer, CAN, SCI, PWM signals. Please check Table 2-1. Pin Functions and Priorities in RM and MODRR0~MODRR3 routing register settings for avoiding routing issues. Be aware that MODRR0~3 register could be written just once in normal mode – all configuration must be written by single register write command.
   The ECLK signal may be enabled/disabled in ECLKCTL register.
3. Please check the transfer width at XFRW bit. Set for 16bit transfers. Clear for 8bit (or any other) transfers.
4. Since the SPI module is set as slave, SPI baud rate register value is irrelevant, but you may check whether the maximum SPI baudrate is lower than bus clock/4 (the limit for SPI slave).
5. I suppose that you don’t use bidirectional mode and SPC0 bit is cleared. Correct?

I hope it helps you.

Have a great day,
Radek