Xgate clock source when in stop modes

[adelantesey]

I'm working on a project using MC9S12XEG128 and I want to take the S12 cpu into full STOP or Pseudo stop mode, but I want the Xgate core to receive data on one of the pins using portH interrupt (Routed to xgate) and a timer.

First of all, I need to know what clock source is available for xgate when the S12 cpu is in full or pseudo stop mode (It seems that xgate uses core clock which seems to be off in stop mode)?

Secondly, what precise timer can I use and how its source clock is provided since the bus clock also seems to be off in stop modes?

[iggi]

Hello,

In Stop mode system clocks are disabled, but there is slight difference between Full Stop and Pseudo Stop modes:

• Full Stop Mode - The oscillator is stopped in this mode. By default all clocks are switched off and all counters and dividers remain frozen. The Autonomous Periodic Interrupt (API) and ATD modules may be enabled to self wake the device.
• Pseudo Stop Mode - In this mode the system clocks are stopped but the oscillator is still running and the real time interrupt (RTI) and watchdog (COP), API and ATD modules may be enabled. Other peripherals are turned off.

But, there is also another mode so called Wait mode and this isn't low-power, but it can significantly reduce power consumption:

• Wait Mode - This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute instructions. The internal CPU clock is switched off. All peripherals and the XGATE can be active in system wait mode. For further power consumption the peripherals can individually turn off their local clocks.

Regarding timers, you can use RTI or maybe better the API module to generate time base on external pin.

VREG_API module can be driven by bus clock or API clock. When bus clock is off (stop mode), APICLK can be selected and the time period can be set to 65356 different values in between 0.2ms and 13107.2ms.

Find more info in the S12XEP100 ref. manual.

See 23.3.2.3, “Autonomous Periodical Interrupt Control Register (VREGAPICL) and 23.4.8, “Autonomous Periodical Interrupt (API) for details.

Regards,

Ivan