XEP100 - SPI1 strange data corruption that appears only in the 112pin package.

[Pedro_]

Hi, the board I am developing software for has a 5554 and a XEP100 processor.
The MPUS are linked using SPI, 5554 is the master.
A total of 32 16bit words are transmitted periodically in continous transfer mode (the select line is kept asserted during transfers).

In the XEP side, SPI 1 is the module used and it has been routed to Port H.
I am experiencing data corruption in the receiving end. It looks like in some of the words, the module has missed a whole clock period and data appear shifted one or two bits.
For testing purposes, the baud rate has been set to around 50KHz and I have verified that the minimum time between transfers is met. I have also looked at the signal to check the correct data is sent from the master.

Now, this is the interesting thing. If I run the exact same software on an eval board (144 pin package) there is NO data corruption. The problem appears when I run the software on a demo board (112 pin package), I have tried two of these.

The question is:
- Is there any difference between the two packages that could produce such issue?
- Is there any errata that I could have missed?

My next test will be to
- try the same software on SPI1 but without routing to Port H.
- try the same software on SPI0

Any suggestion?

Thanks
Pedro.

[Pedro_]

Further to it.

I tried using SPI0 and SPI2 (currently on SPI1) and the problem persists in the 112LQFP but works fine in the 144LQFP.

The issue is definetly related to writing into the Data Register, which is done in 16 bit access.

If I write 0x00 on each SPTEF interrupt, there is no corruption in the incoming data. If I write a value different from 0x00 on one or more of the SPTEF interrupts, the corruption appears.

As mentioned before, the system is set up so the SS line remains low during the whole transfer. Both master and slave are shifting data out. The configuration is CPHA = 1 in order to allow it.

I am trying to understand what could be the differences between the 144LQFP and 112LQFP I have on my test boards.

The numbers written on the chips are:

PC9S12XEP100MAL (112 LQFP)

CV2412.20

4M48H

QQAA0738

PC9S12XEP100VAG (144 LQFP)

CV2589.09

4M48H

QQAD0749

How can I check if the silicon in those chips are the same?

thanks

Pedro

[peg]

Hi,

I don't know this device at all, but as the mask no. (4M48H) is the same I would think the silicon should be the same in both.

[Pedro_]

Hi all,

finally, the root cause of the problem has been found so I thought I let you know.

The corruption in the received data was caused by noise in the chip select line.

That is the reason why the corruption was perceived as bits shifted.

The MISO line from the XEP was connected directly to the 5554 (no resistor in between), the edges in this line were producing a ~4 ns 2.2v spike in the SS line.

The reason why the problem appeared in one and not in the other board (EV9S12XEP100 & DEMO9S12XEP100)  was surely related to the layout.

Regards