XEP100 EEEPROM

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XEP100 EEEPROM

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johnthompson001
Contributor II

I notice in the EEEPROM_Quick_Start.mcp project in the main.c code there is the line..

#define PARTITION_D_FLASH 0x20  /* M48H mask only */

As I am using a different mask (1N35H) could  someone tell me how the PARTITION should be modified.

We are using the DEMOAX9S12 evaluation board with the XEP100 device and using the EEEPROM_Quick_Start.mcp  project from the downloaded AN3743SW.zip files. I am able to verify the EEEPROM memory functionality by stepping through the code using Codewarrior when connected to the Demo board but when trying to repeat the process on our design of system board with a XEP100 then the FDIV error is displayed whilst executing the step through. I've confirmed the  

 

'#define FCLK_DIV 0x2F   // Flash clock divider for 50MHz crystal'

 

in the CLOCK DIVIDE SECTION is correct and the board/device functions correctly with the rest of the project. This is the second system board with an XEP100 device showing the same problem so I'm confident I've ruled out a device with faulty memory.

Any ideas?

28 Replies

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johnthompson001
Contributor II

Hi Radek,

Thanks for coming back to me.

Is this the information you require below.

Regards

John

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi John,

Could you please elaborate on what exactly doesn't work? Do you see any error flags? Which Flash operation sets the flags?

Just to be sure, the external oscillator is 1.8V CMOS compatible, and you can measure correct bus clock frequency (max 50MHz) on ECLK pin, right?

 

Regards,

Daniel 

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johnthompson001
Contributor II

Hi Daniel,

The crystal oscillator is HCMOS/TTL compatible reduced to a 2.2 v amplitude signal and confirmed at 50MHz.

Regards

John Thompson

Testometric

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johnthompson001
Contributor II

Hi Radek,

I feel I’m missing something obvious here.

If I connect to the Demo board (50MHz clock) and launch the EEEPROM Quick Start project I see the following memory:

When I connect to our board (20MHz clock) and launch the project on our board I see the following:

I’ve verified the FCLK_DIVIDE is set correctly.

I don’t see any errors whilst stepping through the code in Debug.

Sorry if I’m missing something obvious.

BR

John

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johnthompson001
Contributor II

Hi Radek,

I’ve tried the EEEPROM Quick Start with a 20MHz oscillator (remembering to alter the FCLK_DIV to 0x13) with no positive change.

XCLKS is pulled down on Reset.

I’ve also tried running the two projects in the attachment (Emulated EEPROM & Initial_data_in_Emulated EEPROM) but I’m not sure what I’m looking for to verify the EEPROM memory is working.

I can send you the schematic if you’ve time to have a quick look although our XEP100 based board works when I load other projects… just not the EEPROM.

BR

John

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johnthompson001
Contributor II

Hi Radek,

Many thanks for your reply.

I’m using a SMD crystal oscillator fed into the Extal input on the XEP100. Interestingly, I’ve installed a 50MHz crystal oscillator on the DemoAX9S12 board and tried the same EEEPROM Quick Start and it worked OK… but it is not the same oscillator! I’ll try a 20MHz oscillator now I’m armed with your information.

Regards

John Thompson

Testometric

materials testing machines

Unit 1, Lincoln Business Park

Lincoln Close, Rochdale

Lancashire, England OL11 1NR

Telephone: +44 (0) 1706 654039

Facsimile: +44 (0) 1706 646089

Website: www.testometric.co.uk<blocked::http://www.testometric.co.uk/>;

Reg. No. 1112862 England

P Please consider the environment before printing this email.

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi,

The difference between 1N35H and 5M48H is only in the fab site not in the silicon.

You can refer to errata of these masksets, they are identical.

https://www.nxp.com/docs/en/errata/MSE9S12XEP100_1N35H.htm

https://www.nxp.com/docs/en/errata/MSE9S12XEP100_5M48H.htm

 

Do you really use 50MHz crystal?

 

The specification of max f_osc is 16MHz with loop-controlled and 40MHz with full-swing Pierce oscillator.

 

Regards,

Daniel

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johnthompson001
Contributor II

Many thanks Daniel.

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