Why does ATD1 appear to not work at all in MC9S12XEP100?

[duanecarter]

I configure both ATD0 and ATD1 in the same way from code ported from a system working with the MC9S12DP256.  All the register settings were modified in the port according to guidance in the S12 / S12XE compatibility guide (AN3469) and the S12XE reference manual (MC9S12XEP100RMV1). Signals connected to ATD0 inputs all result in expected A/D conversion values.  Nothing connected to ATD1 inputs comes close to correct.  In fact, all inputs yield a very similar result, a little less that the midrange of 10-bit, regardless of the voltage level of the input signal (5V A/D reference, inputs of 4.1V, 2.5V, ground, and floating open).

[Martin35804]

Hi,

try the below ATD1 init function. There is PLL init function as well at the end.

void init_ATD1(void)
{
  ATD1CTL1 = 0B01010000; // ATD Control register 1
                        // Bit 7 = External trigger source select - 0 is an A to D channel
                        // Bit 6,5 = A/D resolution select - '10' is 12 bit
                        // Bit 4 = Discharge before sampling bit - enabled
                        // Bit 3,2,1,0 = External trigger channel select - 0 (with bit 7) is AN0


  ATD1CTL2 = 0B00000000; // ATD Control register 2
                        // ICLKSTP set, allows A to D clock to run in stop.  ATD Compare interrupt enabled */
                        // Bit 7 = Not Implemented
                        // Bit 6 = ATD Fast Flag Clear all - disabled
                        // Bit 5 = Internal clock in stop mode - disabled
                        // Bit 4 = External trigger level / edge control - not relevant
                        // Bit 3 = External trigger polarity - not relevant
                        // Bit 2 = External trigger mode enable - disabled
                        // Bit 1 = ATD Complete interrupt enable - disabled
                        // Bit 0 = ATD Compare interrupt enable - disabled


  ATD1CTL3 = 0B10000010; // ATD Control register 3
                        // Bit 7 = DJM (Data Justification) - 0/1 is left/right justified
                        // Bit 6,5,4,3 = Conversion sequence length - '0000' (16 conversions / sequence)
                        // Bit 2 = result register FIFO mode - 0 for non-fifo
                        // Bit 1,0 = Background debug freeze enable - '10' finish current conversion then freeze

#if PLL==1
  ATD1CTL4 = 0x02;      // ATD Control register 4
                        // Bit 7,6,5 = Sample time select - '000' is 4 ATD clock cycles
                        // Bit 4,3,2,1,0 = ATD Clock prescaler - '00010' clk freq = fbus/(2*(2+1)) = 50MHz/(2*(2+1) = 8.33 MHz #else
  ATD1CTL4 = 0x00;      // ATD Control register 4
                        // Bit 7,6,5 = Sample time select - '000' is 4 ATD clock cycles
                        // Bit 4,3,2,1,0 = ATD Clock prescaler - '00000' clk freq = fbus/(2*(0+1)) = 8MHz/(2*(0+1)) = 4 MHz #endif 


  ATD1DIEN = 0x0000;    // ATD Input enable register
                        // Bit 15 - 0 = ATD digital input enable on channel n - (not enabled on any channel)

  ATD1CMPE = 0x0000;  // ATD Compare enable register
                      // Bit 15 - 0 = Compare enable for conversion number n

  ATD1CMPHT = 0x0000;  // ATD compare higher than register
                      // Bit 15 - 0 = compare operation higher than enable for conversion number n - (compare if higher than for n = 0)

  ATD1CTL5 = 0B00110000;// ATD Control register 5 (Write clears conversion complete flag in ATD1STAT2)
                      // Special channel conversion disabled, continuous conversion enabled, multi mode disabled.  Lower nibble sets channel 0 */
                      // Bit 7 = Not implemented
                      // Bit 6 = Special channel conversion bit - disabled?
                      // Bit 5 = SCAN (Continuous conversion sequence mode) - enabled
                      // Bit 4 = Multi channel sample mode - enabled
                      // Bit 3,2,1,0 = Analog input channel select code - '0000' is AN0

}
//******************************************************************************
void init_PLL(UBYTE _synr, UBYTE _refdv,UBYTE _postdiv) {


    PLLCTL  = 0B00000001;                  // clock monitor - off
                                            // PLL - off
                                            // VCO modulation  00-Off,01-1%,10-2%, 11-4%
                                            // fast wake up - off
                                            // RTI - off
                                            // COP - off
                                            // SCM - on

    CLKSEL  = 0B00100011;                  // clock = OSCCLK
                                            // pseudo stop - off
                                            // external clock used (canned oscillator)
                                            // 0
                                            // PLL in wait mode - on
                                            // 0
                                            // RTI in wait - off
                                            // COP in wait - off


    SYNR    = _synr ;
    REFDV  = _refdv;
    POSTDIV = _postdiv;



    PLLCTL_PLLON = 1;                        // PLL - on
    PLLCTL_CME  = 1;                        // clock monitor - on

    while(!CRGFLG_LOCK);                    // Wait till the PLL VCO is within tolerance
    CLKSEL_PLLSEL = 1;                      // Select clock source from PLLCLK
}
//******************************************************************************

[duanecarter · Accepted solution]

Thanks for the help, but my local FAE pointed out that the 112-pin package I am using for this part doesn't bond out ATD1.  All 16 inputs are now connected only to ATD0.