Unimplemented Instruction

[rhb3]

I am testing the checksum feature of the automatic linker (banked memory too so _CHECKSUM_USE_FAR_PTR is defined). To do this I'm taking my *.sx file and corrupting it prior to converting to a *.phy file and flashing to ensure my checksum code works.

Case 1: When corrupting the data field of an instruction everything works.

Case 2: When corrupting an instruction (say CLRB to NOP) everything works

Case 3: This is where it's not working so well! I take a known section of code that I can control running via the interface and I corrupt some code byte to an illegal op code (say 0x8D). At startup the system notified me of the error as expected. The application continues. I fore the section with the illegal op code to execute. I have a handler for the unimplemented instruction. This handler is basically

for ( ; ; ) {
_FEED_COP();
PORTK_BIT0 = 1;
}

Now, what's strange is that the system resets. The COP doesn't automatically reset the system on an illegal op code does it? Any other thoughts (I'm pretty certain my vector table is setup correctly and the ISR is located in non-banked)?

Thanks!

Message Edited by rhb3 on 2006-12-0102:45 AM

[CompilerGuru]

Cool, you got the checksum working :smileyhappy:
(there was another thread about this
previous thread)

About this one, for a HC12, an opcode of 0x8D is for an CPY #Imm instruction, it is not an illegal opcode. So which instruction bytes do you actually execute, what happens, and what did you expect?
For me this sounds like a good example where just assembly stepping through the code and watching would be the simplest thing to do.

In the end, once the checksum failed, not sure how reasonable it is to execute the code anyway. Well, it probably depends a lot on what your application is for.

Daniel

[J2MEJediMaster]

When the processor (I'm assuming HC(S)12 here) executes that corrupted code, it might trigger an exception other than an unimplemented instruction. Have you tried seeing if another type of interrupt is firing?

---Tom

[rhb3]

No I haven't.  Here's my vectors:

Code:

/*lint -e(950) */typedef void (*near tIsrFunc)(void);/*lint -e(950) */const tIsrFunc _vect[] @0xFF80U = {        /* Interrupt table */    /* Interrupt Vectors */        Unimplemented_ISR,                 /* 0 Default (unused) interrupt, address 0xFF80 */        Unimplemented_ISR,                 /* 1 Default (unused) interrupt, address 0xFF82 */        Unimplemented_ISR,                 /* 2 Default (unused) interrupt, address 0xFF84 */        Unimplemented_ISR,                 /* 3 Default (unused) interrupt, address 0xFF86 */        Unimplemented_ISR,                 /* 4 Default (unused) interrupt, address 0xFF88 */        Unimplemented_ISR,                 /* 5 Default (unused) interrupt, address 0xFF8A */        Unimplemented_ISR,                 /* 6 Default (unused) interrupt, address 0xFF8C */        Unimplemented_ISR,                 /* 7 Default (unused) interrupt, address 0xFF8E */        Unimplemented_ISR,                 /* 8 Default (unused) interrupt, address 0xFF90 */        Unimplemented_ISR,                 /* 9 Default (unused) interrupt, address 0xFF92 */        Unimplemented_ISR,                 /* 10 Default (unused) interrupt, address 0xFF94 */        Unimplemented_ISR,                 /* 11 Default (unused) interrupt, address 0xFF96 */        Unimplemented_ISR,                 /* 12 Default (unused) interrupt, address 0xFF98 */        Unimplemented_ISR,                 /* 13 Default (unused) interrupt, address 0xFF9A */        Unimplemented_ISR,                 /* 14 Default (unused) interrupt, address 0xFF9C */        Unimplemented_ISR,                 /* 15 Default (unused) interrupt, address 0xFF9E */        Unimplemented_ISR,                 /* 16 Default (unused) interrupt, address 0xFFA0 */        Unimplemented_ISR,                 /* 17 Default (unused) interrupt, address 0xFFA2 */        Unimplemented_ISR,                 /* 18 Default (unused) interrupt, address 0xFFA4 */        Unimplemented_ISR,                 /* 19 Default (unused) interrupt, address 0xFFA6 */        Unimplemented_ISR,                 /* 20 Default (unused) interrupt, address 0xFFA8 */        Unimplemented_ISR,                 /* 21 Default (unused) interrupt, address 0xFFAA */        Unimplemented_ISR,                 /* 22 Default (unused) interrupt, address 0xFFAC */        Unimplemented_ISR,                 /* 23 Default (unused) interrupt, address 0xFFAE */        Unimplemented_ISR,                 /* 24 Default (unused) interrupt, address 0xFFB0 */        Unimplemented_ISR,                 /* 25 Default (unused) interrupt, address 0xFFB2 */        Unimplemented_ISR,                 /* 26 Default (unused) interrupt, address 0xFFB4 */        TI1_Interrupt,                     /* 27 Default (unused) interrupt, address 0xFFB6 */        Unimplemented_ISR,                 /* 28 Default (unused) interrupt, address 0xFFB8 */        Unimplemented_ISR,                 /* 29 Default (unused) interrupt, address 0xFFBA */        Unimplemented_ISR,                 /* 30 Default (unused) interrupt, address 0xFFBC */        Unimplemented_ISR,                 /* 31 Default (unused) interrupt, address 0xFFBE */        Unimplemented_ISR,                 /* 32 Default (unused) interrupt, address 0xFFC0 */        Unimplemented_ISR,                 /* 33 Default (unused) interrupt, address 0xFFC2 */        Unimplemented_ISR,                 /* 34 Default (unused) interrupt, address 0xFFC4 */        Unimplemented_ISR,                 /* 35 Default (unused) interrupt, address 0xFFC6 */        Unimplemented_ISR,                 /* 36 Default (unused) interrupt, address 0xFFC8 */        Unimplemented_ISR,                 /* 37 Default (unused) interrupt, address 0xFFCA */        Unimplemented_ISR,                 /* 38 Default (unused) interrupt, address 0xFFCC */        Unimplemented_ISR,                 /* 39 Default (unused) interrupt, address 0xFFCE */        Unimplemented_ISR,                 /* 40 Default (unused) interrupt, address 0xFFD0 */        Unimplemented_ISR,                 /* 41 Default (unused) interrupt, address 0xFFD2 */        outside_incoming_isr,              /* 42 SCI1 isr, address 0xFFD4 */        disp_incoming_isr,                 /* 43 SCI0 isr, address 0xFFD6 */        Unimplemented_ISR,                 /* 44 Default (unused) interrupt, address 0xFFD8 */        Unimplemented_ISR,                 /* 45 Default (unused) interrupt, address 0xFFDA */        Unimplemented_ISR,                 /* 46 Default (unused) interrupt, address 0xFFDC */        Unimplemented_ISR,                 /* 47 Default (unused) interrupt, address 0xFFDE */        Unimplemented_ISR,                 /* 48 Default (unused) interrupt, address 0xFFE0 */        Unimplemented_ISR,                 /* 49 Default (unused) interrupt, address 0xFFE2 */        Unimplemented_ISR,                 /* 50 Default (unused) interrupt, address 0xFFE4 */        Unimplemented_ISR,                 /* 51 Default (unused) interrupt, address 0xFFE6 */        Unimplemented_ISR,                 /* 52 Default (unused) interrupt, address 0xFFE8 */        Unimplemented_ISR,                 /* 53 Default (unused) interrupt, address 0xFFEA */        Unimplemented_ISR,                 /* 54 Default (unused) interrupt, address 0xFFEC */        Unimplemented_ISR,                 /* 55 Default (unused) interrupt, address 0xFFEE */        Unimplemented_ISR,                 /* 56 Default (unused) interrupt, address 0xFFEE */        Unimplemented_ISR,                 /* 57 Default (unused) interrupt, address 0xFFF2 */        Unimplemented_ISR,                 /* 58 Default (unused) interrupt, address 0xFFF4 */        Unimplemented_ISR,                 /* 59 Default (unused) interrupt, address 0xFFF4 */        illegalopcode_ISR,                 /* 60 Illegal Op Code (unimp instruction ISR) */    /* Reset Vectors (vectors here after reset!) */    /*---------------------------------------------------------------------------+     |                                                                           |     |   COP Watchdog Reset 3 CRG Module 0xFFFA, 0xFFFB                          |     |                                                                           |     |   Clock Monitor Reset 2 CRG Module 0xFFFC, 0xFFFD                         |     |                                                                           |     |   External Reset 1 RESET pin 0xFFFE, 0xFFFF                               |     |   Power-on Reset 1 CRG Module 0xFFFE, 0xFFFF                              |     |   Low Voltage Reset 1 VREG Module 0xFFFE, 0xFFFF                          |     |                                                                           |     +--------------------------------------------------------------------------*/        _SystemReset,                      /* 61 Default (unused) interrupt, address 0xFFFA */        _SystemReset,                      /* 62 Default (unused) interrupt, address 0xFFFC */        _EntryPoint                        /* Reset vector, address 0xFFFE */   };

 
So most of my unused ISRs go to Unimplemented_ISR which only has a RTI.  That's why I was wondering if the COP was somehow resetting through 0xFFFA?  I haven't read any documentation to suggest the COP would reset on an illegal op code though.

[rhb3]

I used some test code to verify it is resetting through another vector.  I'm uncertain which one or why; however, it is NOT the COP reset as I have a flash variable that counts "abnormal resets" (clock and COP).  BTW, it is a hcs12.  All other ISRs go to Unimplemented_ISR() which is RTI only.  I suspect SWI as it handles the return address differently but that should come via an instruction only.

Thanks