There meet a question about HCS12 Chip's SCISR1Register

[xianyu]

When I debug my uart process,I found my uart process  runs unusual.

Then I found the SCISR1's OR bit can not be clear and set with out RDRF bit set.

Usual when RDRF bit and OR bit set at the same time I can clear them all by read scisr1 regiser and scidrl

But I check datasheet I can't find the discrib about this abnormal situation.

[dianabatrlova]

Hello,

Does this problem appear only in the case of debugging?

Unfortunately, you did not specify the concrete MCU.

So, at first, I would like to recommend you to look at the similar threads available on the community:

SCI - OR flg but no RDRF 

Debuuging SCI RDRF bit in Codewarrior 

For example, If you have S12G MCU you can find the description OR flag in the Reference Manual rev. 1.27:

"Note: OR flag may read back as set when RDRF flag is clear. This may happen if the following sequence of
events occurs:
1. After the first frame is received, read status register SCISR1 (returns RDRF set and OR flag clear);
2. Receive second frame without reading the first frame in the data register (the second frame is not
received and OR flag is set);
3. Read data register SCIDRL (returns first frame and clears RDRF flag in the status register);
4. Read status register SCISR1 (returns RDRF clear and OR set).
Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy
SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received."

I hope it helps.

Best Regards,

Diana