Hi, no, not only input capture. The MODRR2 is good to be read step by step and think abot function. Some of them are really input only because they connect internally the pin to another peripheral input for specific application functions.
The PT2 pin #52 at 64pin LQFP can be used for PT2 / IOC0_2 / (PWM0_5) / (SCK0) with the peripheral priority from left (lowest) to right (highest) as can be seen in the table 1-8 Pin Summary. If more than one peripherals are enabled at the pin the enabled peripheral with the highest priority takes precedence over all others.
As you can see from the picture it has also no special connections to other peripherals. So, MODRR can be excluded from considerations.
Of course other peripherals can be routed to this pin (PWM0_5) / (SCK0)
By default MODRR2 the PT2 contains TIM0 IOC_2 connected to the pin if IOC function is enabled. The IOC2 can be rerouted to PS1 in this register if you want but this is not the case.
Both functins are available at the pin ... IC or OC.
To sum up, do nothing just enable TIM and it will be connected to PT2 by default.
But, how to make sure that the previous event action is done or completed ?
- This is an application issue and time you spent in the interrupt routine. There is no specific flag to get it.
Hmmm, there is. If you clear the flag at the beginning of the interrupt and at the end of the function it is set again then you were there longer than time between two interrupts. The interrupt is then generated again.
Is there any way to check if PT2 pin Output is High or Low ?
- Yes, you can connect it also to another pin externally to get this info (polling) plus you can put it to two pins selected for interrupt on rising edge and the other one for falling edge and both will set some variable in interrupt. Or you can put it to another Timer channel and set it for capture on both edges. The setup of TFFCA can influence the moment of the clering flag. never combine clearing flag automatically with manual clearing. It leads to issues.
One more thing, 11.3.2.4 Timer System Control Register 1 (TSCR1) ... for debugging purposes set the bit TSFRZ
Timer Stops While in Freeze Mode. ....it means timer follows your stepping and when debug mode is active timer stops and runs only between steps or breakpoints.
Best regards,
Ladislav.
