Single channel multiple conversion about S12G ADC

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Single channel multiple conversion about S12G ADC

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Contributor III

Hi,

I try to use ADC of S12G128 to read the average value of the analog signal whoes period is about 100us. I hope that a channel can complete 10 conversions in 100us, and the time interval of each conversion is 10us. Does the MCU support such application?

Best Regards,

Jeff

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3 Replies

32 Views
NXP TechSupport
NXP TechSupport

Hi,

There is no automatic timing on given period implemented.

There is an ATDCTL3 register which contains bits providing number of conversions in one sequence. However, it does not considers period between conversions. You are able to set up to 12 conversions in a one sequence.

What you have to do is set an interrupt after each conversion and store data to some data buffer/array.

The question is whether it is not more simpler to perform 10 single conversions and process them individually. The conversion time is 3us.

The best solution I see is to run ATD in continuous mode when it converts channel in an automatic never-ending loop and set a timer for interrupt in which data are read and stored.

 

Simple example (immediate idea, not tested).

 

Unsigned char cnt, data, sequence_in_progress=false;

 

Void interrupt Timer_interrupt(void)

{

    Data[cnt] = ATDDRxL;

    cnt--;

    if(!cnt) Stop_sequence();  // stop interupt from timer

}

 

Start_sequence(void)

{

   cnt=10;

   sequence_in_progress = true;

   enable_interrupt_from_timer()

}

 

Void main(void)

{

For(;;)

  {

     Start_new_sequence();

     While(sequence_in_progress=true) ;

     Process_data()

   }

}

 

Another solution could be to start manually each conversion with given period. The question is data processing time.

The S12G is very simple and low cost MCU assigned for specific simple tasks. It does not contain special features. For such a task would be better to use some more complexs MCU (more expensive). For example S12XE, S12XD provide parallel XGATE interrupt oriented core, big set of timers, higher BUSCLK.

Finally, data storage, manipulation and processing will be main limitation factor in your application. I am no table to say how much time you will need for that (Max BUSCLK = 25MHz...40ns....approximately 150cycles for data manipulation and control)

Best regards,

Ladislav

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32 Views
Contributor III

Hi Ladislav,

Thanks for the reply. 

I want to do by the following step:

1. fBUS=25MHz  fATDCLK=fBUS/(2*(PRS+1))=25MHz/(2*(4+1))=2.5MHz(It is in the range of 0.25 to 8MHz)

2. The sample time is set to 10(SMP[2:0]=3), so the total conversion time is about:

Nconv10=Ndis+Nsample+15=0+10+15=25 ADC clock cycle=25*1/2.5MHz=10us(According to AN4558 Eqn.5)

3. Set 10 conversions per sequence

 

Then I will get 10 conversion results per sequence. Do you think it is feasible?

Best Regards,

Jeff

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32 Views
NXP TechSupport
NXP TechSupport

Hi,

ATDCTL3_FIF0.....

0 Conversion results are placed in the corresponding result register up to the selected sequence length.

1 Conversion results are placed in consecutive result registers (wrap around at end).

 

There are 8 result registers plus ATDCTL_SxC enables to set maximally 8 conversions in one sequence so max 8 results can be stored in one sequence .

I think 8 results is enough for calculation of average.

Best regards,

Ladislav

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