S912ZVL64F0VLCR question

[Caleb1]

Using a PNP transistor to connect VDDA and VDDX, the value of VDDX is 2.9V, the input is 11.35V, and the BCTL is also 11.35V. Do you want to confirm what causes the output voltage of VDDX to be incorrect?

[danielmartynek]

Hi @Caleb1,

I understand you have the S12ZVL64 not S912ZVL(A)64, and CPMUVREGCTL = 0x02 that mean the internal regulator is disabled and VDDX is expected to be 5V.

What kind of transistor do you use?

High hFE transistors in this regulator can be switching between cut-off and saturation.

AN5084: Hardware Design Guidelines for S12ZVL provides a list of recommended transistors.

https://www.nxp.com/webapp/Download?colCode=AN5084

Do you use the 1kohm stability resistor between the emitter and the base, and the recommended 4.7uF – 10uF VDDX stability capacitor?

What is the power consumption of the MCU?

Thank you,

BR, Daniel

[Caleb1]

The current client's schematic design is the same as the schematic design provided

Adverse phenomenon: The normal output voltage of VDDX is 5V, but now it is 2.906V. The circuit behind this pin has been disconnected

Defective rate: The customer produced 60 sets and encountered 2 sets of this issue. If the power is cut off and then turned on again, the fault will disappear. I have done hundreds of power ups and downs, and this bad phenomenon will recur seven or eight times

The customer uses a normal board, erases the chip code, and then powers it on again. The output voltage of VDDX is 3.3V

[danielmartynek]

Hi @Caleb1,

The Low-voltage reset asserts typically at 3.02V VDDX.

Can you monitor VDDX along with the Reset pin using an osciloscope? I assume the MCU is being periodically reset when you measure VDDX = 2.9V.

Please share the schematic and the whole project or a test code that you can reproduce it with.

If you don't want to share it here publicly, create a ticket.

What is the power consumption of the MCU at VSUP when VDDX = 5V and 2.9V?

Regards,

Daniel