S12ZVL64 Bootloader problems

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S12ZVL64 Bootloader problems

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fanziyu
Contributor III

Hello,I have some problems when i studying bootloader.

MCU:MC9S12ZVL64

1:AN4723,4.3 Memory erase. "the bootloader must be placed on the last sectors of the P-FLASH array(right before the last sector)". Is this advice or a rule?  what will happen if there is a sector between last sector(0xFFFE00 TO 0xFFFFFF) and bootloader?

2:P-Flash Erase and P-Flash write functions must be executed from RAM. In AN4723,these functions on SHADOW_ROM_S are copied to RAM to execute. Can i use the following method instead? 

#pragma CODE_SEG DEFAULT_RAM

void PFLASH_Erase_Verify_Section(void) { ... }

3:In main application,how to configurate the linker file if i move the interrupt table from its default position?

which one is right?

ROM = READ_ONLY 0xFF0000 TO 0xFFE5FF;

or ROM = READ_ONLY 0xFF0200 TO 0xFFE5FF;

In this case, how to decide the main application entry address?  0xFF0000 or 0xFF0200?

In this case,There are two vector tables in the current program ,one for bootloader one for main application,is that right?

4: I know bootloader ROM address and the main application addresses must not overlap. Following is wrong.

ROM = READ_ONLY 0xFF0000 TO 0xFFFDFF;//bootloader prm

------------------------------------------------------------------------------------------------------

ROM = READ_ONLY 0xFF0000 TO 0xFFFDFF;//the main application prm

 

But i am not sure that is it wrong for RAM configuration.

RAM = READ_WRITE 0x001000 TO 0x001FFF;//bootloader prm

--------------------------------------------------------------------------------------------------

RAM = READ_WRITE 0x001000 TO 0x001FFF;//the main application prm

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StanoA
NXP Employee
NXP Employee

Hello Fanziyu,

As described in AN4723 the ROM starts from top address 0xFFFFFF and goes down to 0xFF0000 for 64kB version. The RAM address starts on 0x001000 and goes up to 0x0013FF for 1k version (0x2000 for 4k version).

The Bootloader has two parts of code – one executed from FLASH and one executed from RAM (the code running during FLASH erase & write process). The last one takes one page (512 bytes). So it must be allocated in FLASH – segment SHADOW_ROM_S (512 b) and also in RAM segment SHADOW_RAM_S (512 b). The code is copied from FLASH to RAM and then executed. It is erase & write function.

This segment has to be in section:

SHADOW_ROM_S = READ_ONLY 0xFFFC00 TO 0xFFFDFF; // 512 bytes;

The Bootloader code executed from FLASH in in section:

ROM_BTLDR = READ_ONLY 0xFFF800 TO 0xFFFBFF;  // 1k bytes;

The rest of ROM is for user code section:

ROM = READ_ONLY 0xFF0000 TO 0xFFF7FF;  // 62k bytes;

For RAM the section for the Bootloader is:

SHADOW_RAM_S = READ_WRITE 0x001000 TO 0x0011FF;  // 512 bytes;

The rest of RAM is for user code:

RAM = READ_WRITE 0x001200 TO 0x0013FF;  // 512 bytes for smallest version;

After RESET the code starts from top FLASH – jump function to start address of Bootloader – this is fix address. The Bootloader code runs and waits 100msec for received data for FLASH program. If not received the time-out take place and program jump to top of FLASH section intended for user code. It is top of page beneath the Bootloader ROM section 0xFFF7FF. This configuration is independent of larger or smaller memory version device.

The best option is to place the new vector table right under Bootloader FLASH section. Then the whole rest of FLASH is free for application code without any segmentation. It is good the protect that BTLDR + next Vector table area by set the protection function. This is most universal solution for whole MCU family because it is valid for all memory versions from small to large versions.

I hope it could help you to solve your task.

Best Regards,

Stano.

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StanoA
NXP Employee
NXP Employee

Hello Fanziyu,

The good rule to use the Bootloader function is to place the BTLDR code to the highest possible FLASH sector. This means right under last sector. The reason is the rest of FLASH is free for user code not matter if small or large memory MCU is used.

The comprehensive information with BTLDR SW is free on web:

https://www.nxp.com.cn/products/processors-and-microcontrollers/additional-mpu-mcus-architectures/s1...

Please try to use it for study or for your application if you want.

I hope it will help you to solve your task.

Best Regards,

Stano.

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StanoA
NXP Employee
NXP Employee

Hello Fanziyu,

As described in AN4723 the ROM starts from top address 0xFFFFFF and goes down to 0xFF0000 for 64kB version. The RAM address starts on 0x001000 and goes up to 0x0013FF for 1k version (0x2000 for 4k version).

The Bootloader has two parts of code – one executed from FLASH and one executed from RAM (the code running during FLASH erase & write process). The last one takes one page (512 bytes). So it must be allocated in FLASH – segment SHADOW_ROM_S (512 b) and also in RAM segment SHADOW_RAM_S (512 b). The code is copied from FLASH to RAM and then executed. It is erase & write function.

This segment has to be in section:

SHADOW_ROM_S = READ_ONLY 0xFFFC00 TO 0xFFFDFF; // 512 bytes;

The Bootloader code executed from FLASH in in section:

ROM_BTLDR = READ_ONLY 0xFFF800 TO 0xFFFBFF;  // 1k bytes;

The rest of ROM is for user code section:

ROM = READ_ONLY 0xFF0000 TO 0xFFF7FF;  // 62k bytes;

For RAM the section for the Bootloader is:

SHADOW_RAM_S = READ_WRITE 0x001000 TO 0x0011FF;  // 512 bytes;

The rest of RAM is for user code:

RAM = READ_WRITE 0x001200 TO 0x0013FF;  // 512 bytes for smallest version;

After RESET the code starts from top FLASH – jump function to start address of Bootloader – this is fix address. The Bootloader code runs and waits 100msec for received data for FLASH program. If not received the time-out take place and program jump to top of FLASH section intended for user code. It is top of page beneath the Bootloader ROM section 0xFFF7FF. This configuration is independent of larger or smaller memory version device.

The best option is to place the new vector table right under Bootloader FLASH section. Then the whole rest of FLASH is free for application code without any segmentation. It is good the protect that BTLDR + next Vector table area by set the protection function. This is most universal solution for whole MCU family because it is valid for all memory versions from small to large versions.

I hope it could help you to solve your task.

Best Regards,

Stano.

View solution in original post

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fanziyu
Contributor III

Due to network reasons, I did not notice that a draft was posted last time called "How to decide the main application fixed address". I am really sorry for that.

I am still confused about some questions.

1:Does the following function still occupy P-FLASH space?Or just occupy the RAM space? I find some explain such as:The function will be automatically copied from Flash to the RAM during Startup().

#pragma CODE_SEG DEFAULT_RAM 
void pflash_send_command(void)
{
...
}
#pragma CODE_SEG DEFAULT
 
2:"If you look into the code the PFLASH_Send_Command function is called in the PFLASH_Erase_Verify_Section function. It is not needed to place the whole PFLASH_Erase_Verify_Section function into RAM"  I wonder why the whole PFLASH_Erase_Verify_Section function will be placed into RAM?just because the PFLASH_Send_Command function is called in it ?There seem to be some rules  that I don’t know.Could you help me ?Thanks a lot!
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fanziyu
Contributor III

One more question:

FSL_LIN_2.x_STACK_Package_4.5.9               lin.h

typedef union {
l_u8 byte; /**< a data byte refer to 8 data bits follow */
struct
{
/* LIN 2.1 */
l_u8 successful_transfer:1; /**< Transfer flag LIN 2.1*/
l_u8 error_in_response:1; /**< Error response LIN 2.1*/
l_u8 bus_activity; /**< Bus activity timeout LIN 2.1*/<------ Is there missing :1 ?
/* J2602 */
l_u8 framing_error:1; /**< frame error flag J2602*/
l_u8 checksum_error:1; /**< checksum error flag */
l_u8 readback_error:1; /**< readback error in J2602 to be called Data Error */
l_u8 parity_error:1; /**< frame error flag */
l_u8 reset:1; /**< reset flag (not implemented) */
} bit;
} lin_status;

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