S12XD document for EEprom programming (S12EETX4KV0)

[Bee]

This may be obvious to some of you, but I can't understand the timing setting of the second example on page 25, using Figure 4-1. The osc. clk is 16 MHz and the Bus clk is 40 Mhz (Tbus=0.025 usec). I get EDIV[5:0]=10 and they get EDIV[5:0]=50. And if I used an osc. clk of 15 MHz, I would get and EDIV[5:0]=5. Where am I going wrong?

[Lundin]

Who are "they"? I quote the EEPROM datasheet:

"If the oscillator clock frequency is 16 MHz and the bus clock frequency is 40 MHz, ECLKDIV bits EDIV[5:0] should be set to 0x0A (001010) and bit PRDIV8 set to 1."

You calculation for 15MHz seems to be wrong though, you should get the value INT(9.42) = 9.

[Bee]

Thanks for your reply. "They" are the writers of the EEprom document (S12EETX4KV0). Apparently we have different versions. Even my Flash programming document has the same example:
"If the oscillator clock frequency is 16MHz and the bus clock frequency is 40MHz, FCLKDIV bits FDIV[5:0] should be set to "50" (110010) and bit PRDIV8 set to "1". The resulting FCLK frequency is then 182kHz."

So the document must have been corrected and I am out of date.

Thank you also for correcting my 15 MHz example.