I´m doing a PWM to DC level converter, and I make the RC filter, and it is good. BUT, the problem is that the edges of the PWM wave generate in others pins of output, a relative high noise (400mV pp). Its continue to occur after I configure the Port P Reduced Drive Register.Before this configuration, the noisewas 850mV pp!!! It´s normal?How can I cancel this noise? Just for info: my PWM output is connectet to base of NPN transistor, by 2K2 resistor. The frequence of PWM is 100KHz, but the noise, is not associated at the frequency, is vary with the rise and fall times of the PWM signal.
The intention is to generate a DC lever to use in a external comparator. ...
If somebody can help me, please... give me a ligth!
I am using s12xs128 mcu and I found out that if External Clock on ECLK pin is disabled the mcu makes much less noise then if output clock in this pin is enabled. I wonder who needs output clock enabled at all. You can simply disable output clock using Device initialization interface where you click on CPU->Output clock->Disabled or make shure that register ECLKCTL bit NECLK = 1.
I hope this will help you.