New to S12X stack frame structure (need assistance) repost

[Xbot]

Hello all,

i would like to read the PC and global page register from the stack, on an event of an access violation interrupt (or perhaps an interrupt in general). I am not familiar with the stack frame structure.

here is what i have initially:

Code:

voidAccessViolation_InterruptHandler(void){

int pc_t;

char gpage_t;

    asm movw 2,sp+7, pc_t;  //im not sure about this

    asm movb 1, sp+6, gpage_t; //this too

}

 i still need to be walked thru the assembler codes as well.

thanks,

[CompilerGuru]

Check this thread:
http://forums.freescale.com/freescale/board/message?board.id=8BITCOMM&message.id=10109

It is for the S08, but for the S12(X) I would do the exactly same thing, of course the struct has to be adapted to the S12X, and the HLI has to be adapted to the S12X too. (transfer the stackpointer to the argument register: TFR SP,D)

Note that there are basically the same challenges for the S12X, as for the S08, the S12 compiler does also reorder the local variables for example. By using a small just HLI function as in the post, all such problems are avoided.

Daniel

[Xbot]

thanks for the help guys, appreciate it...

[kef]

Immediately after CPU stacks its registers and jumps to your AccesViolation ISR (before any function prolog, before allocating variables on stack etc), CPU12X stack frame looks as follows:

PC @ SP+8 , 16bit CPU return address,

Y @ SP+6

X @ SP+4

B:A @ SP+2

CCRH:CCRL @ SP

No page registers (GPAGE, PPAGE, etc ) are stacked when servicing interrupts. You can read GPAGE directly from GPAGE register.

The rest depends on your compiler and version of your compiler. Compiler can allocate 3 bytes on stack for your char and int variables, it may also decide to allocate some temporary variables on stack, above your vars or below. So we can only guess what is offset to PC return address on stack. Try disassembling you code and see what is that offset. For example it could be something like that:

AccessViolation_InterruptHandler:

           leas -3,sp  ; allocating pc_t and gpage_t on stack

           ; if offset is really +3, then

           movw  8+3,SP,  pc_t

           movb   GPAGE, gpage_t

[Xbot]

hi,

Im using cw4 by the way.

from your code "movw  8+3,SP,  pc_t" -- the first parameter of this instruction is the offset of the second?

 how about in this code:

MOVW     2,X+ , 2,-Y  -- can you please explain

thanks,

[kef]

---

Xbot wrote:

Im using cw4 by the way.

from your code "movw  8+3,SP,  pc_t" -- the first parameter of this instruction is the offset of the second?

---

the fisrt parameter (8+3,SP) , the source argument of movw, is a ISR return address on stack, provided CW allocated 3 bytes on stack for local variables. I don't know this figure in advance, it depends on a lot of factors. If both your variables are used in the code and aren't optimized out, then chances are CW is issuing "LEAS -3,SP" and my gues is valid. You should disassemble your code and check what compiler is doing with stack.

And pc_t is your pc_t variable. CW will replace pc_t with something like ?,SP.

---

Xbot wrote:

 how about in this code:

MOVW     2,X+ , 2,-Y  -- can you please explain

---

I'm not sure what are you asking to explain? Are you wondering what above instruction means? Well, predecrement Y register by 2, move a word from memory at X to memory at Y, then postincrement X by two. I welcome you reading CPU reference manual:

http://www.freescale.com/files/microcontrollers/doc/ref_manual/S12XCPUV2.pdf?fpsp=1

Regards