Maximum PWM Frequency achievable on S12Z

[manishsangram]

Hello,

We are using S12ZVMC128 chip for our motor application. Our motor is a 7PP BLDC motor.

We are using simple BEMF based commutation (not FOC).

We want to increase PWM frequency to the maximum possible for reducing torque ripple.

We can't seem to go above 100,000 Khz (PMFMODA 1000). This 100Khz works properly at about 3000 RPM, but fails when we cross about 5000 RPM. At 5000 RPM and higher (till 7500 RPM) we have to switch to 33Khz.

1) We can't figure out why higher RPM requires us to reduce PWM frequency, we can understand if lower RPM requires this as BEMF drops due to lower angular velocity with short pulses.

2) What is the highest PWM practically achievable with S12Z? We would like to go to 200Khz if possible but motor immediately stalls below 110Khz (PMFMODA 900/800) at any RPM. (We have tried to reduce computation load by reducing current sense code, even commenting it out, but it has had no impact)

3) We are using 100Mhz clock speed (50Mhz bus speed). PMF Timer Prescaler is default. We think this implies 100Mhz as the clock speed for PMF. The documentation for S12Z is a bit confusing because in some places they mention fBus and in some places Tcore as the clock source for PMF. 

4) The Dead Time is in PMF clock cycles right? What should the value be if we want 20ns?

Any help here would be highly appreciated.

[pachamatej]

Oh, I can see the confusion:

Figure 15-1 and the whole chapter 15 refers to the PMF module (pulse-width modulator with fault protection), while Table 22-8 and the whole chapter 22 describes 8-channel pulse-width modulator, which is available only for S12ZVMC256 (see Table 1-2).

The ADC timing is given by each command according to Figure 9-28. The time you should be focusing on is the Total sample time. Just to make it easy, the shortest sample time is given by ADC_CLK * (SMP + 4) [Table 9-26], for SMP = 0 means ADC_CLK * 4, thus 1/8.3333MHz * 4 = 0.48us.

In other words, if your ADC sampling exceeds the window in which the signal is available, the ADC would sample some noise or ringing or simply a corrupted signal. Based on that wrong information, the control algorithm may force the motor to stall.

Let's take your 100kHz as an example, with PWM period of 10us. If the reference voltage is set for 95% duty cycle (a usual value if you are reaching the nominal speed), you have just 0.5us for sampling. But this is really highly simplified situation - there are transients (ringing) present near the edges of the switching, which overlaps with your sampling time and may be "visible" to the sample&hold capacitor.

Finally, there may be some propagation delay in the process of ADC triggering, causing the trigger is slightly delayed from what you are expecting (see the PTU description in the RM).

Best regards,

Matej

[manishsangram]

Let's take your 100kHz as an example, with PWM period of 10us. If the reference voltage is set for 95% duty cycle (a usual value if you are reaching the nominal speed), you have just 0.5us for sampling.

Hi MatejPacha‌, I didn't follow why we have only 0.5us ?

If the duty cycle is 95%, if we start sampling after 80% (as in our case) from the start of the pulse we would start at 7.6us thus 2us for sampling DC Bus & BEMF which is plenty of time Since BEMF is measured during the pulse. Am I misunderstanding something here? We will have a problem as the pulse width reduces below 5us I guess.

[pachamatej]

Hello,

I just took one use case which might not be applicable to your case, but explains situation when high frequency PWM may be a limitation in terms of ADC sensing. If you are sensing during the pulse, then it's probably ok.

Anyway (and in any case), have you tried to make a snapshot of your signal along with the PTU trigger signal? PTU can generate trigger signals in debug mode and the signal can be evaluated in terms of ringing. The current signal should be measured at the output of the opamp, BEMF voltages on the phases, DC bus voltage on the HD pin => I still suspect the ADC signal is not sampled correctly.

If the signal is ok, it might be loss of commutation (e.g. due to interrupt overflow, which can be partially solved by assigning higher priority to the commutation event).

Another reason might be the overcurrent comparator - even if the average current is within limits, there still can be some ringing on the signal, which might trigger the overcurrent event and based on the action, it might disable the motor. It would be indicated by the GDUF flags.

And for example, if the low-side MOSFETs are not switched on for sufficient amount of time, based on the bootstrap circuitry design, the bootstrap capacitors might not be fully charged, which may lead to the high side MOSFETs to lose one or more switches (it highly depends on the hardware desing - if you have your own, it is probably designed correctly, but for the development kit / EVB, I would be careful about the operation at high PWM frequencies).

Please let me know how the investigation goes.

Regards,

Matej

[pachamatej]

Hello,

Let me comment to your questions one-by-one:

Ad 1) I believe you are sensing current and voltage. Have you calculated the ADC trigger points and if your ADC sampling fits within one pulse? What is your ADC timing setting in terms of sample&hold interval?

Ad 2) Actually, I don't have any experience with frequencies higher than 40 kHz. Your 200 kHz is not a very common use-case and the device was not designed for it, however, I will be very happy to hear if it works. The device was originally designed for BLDC 6-step commutation and yet it handles FOC with no problems. If you are experiencing stall errors, I would recommend to go to my first comment and check whether the ADC information is correct.

Ad 3) PMF is using core frequency as the input (see RM Figure 15-1)

Ad 4) Since I'm not familiar with the complete timing settings, I would start with the core frequency calculation.

But for 100 MHz core clock and prescaler = 1, the DTMA should be 2 in order to achieve 20ns - according to the Eqn. 15-1 of the RM. Anyway - I would recommend to study the PMF deadtime insertion and possible delays on the way - resulting deaditme may be slightly different.

Please let me know how it goes.

Best regards,

Matej

[manishsangram]

Hi MatejPacha‌

3)  RM Figure 15-1 does mention Core Clock, but Table 22-8. Clock A or Clock B Prescaler Selects refers to bus clock

For ADC, the Sample value is default 0 so it is 4 ADC clock which is running at the max 8.333Mhz. I am not sure how to set the hold time.