MC9S12ZVM128 SRAM double bit ECC handling

[MarkShen__]

We are using the MC9S12ZVM128 and would like to know how to handle double-bit ECC errors in SRAM. Specifically, can the system return to normal operation by performing a software restart using CPMUCOP = 0x01; CPMUARMCOP = 0x00;?

[lama]

Hi,

Let me take it generally.

During POR, the SRAM is initialized. If a double-bit ECC error is detected:

The memory access is blocked.

The initiator module is informed.

7.3.4 Memory Initialization …

To avoid spurious ECC error reporting, memory operations that allow a read before a first write (like the read-modify-write operation of the non-aligned access) require that the memory contains valid ECC values before the first read-modify-write access is performed. The ECC module provides logic to initialize the complete memory content with zero during the power up phase. During the initialization process the access to the SRAM is disabled and the RDY status bit is cleared. If the initialization process is done, SRAM access is possible and the RDY status bit is set.

1. POR (Power-On Reset)

What it does: A POR is a full hardware reset triggered by cycling the power or by a dedicated POR signal.

Effect on ECC error:

- SRAM is cleared: All volatile memory is lost, including the corrupted data.

- ECC logic is reset: Any ECC error flags or status bits are cleared.

- Registers reset to default: All configuration registers return to their default state.

- Implication: The system starts fresh, and the double-bit ECC error will not persist unless the same corrupted data is reloaded from flash or external sources.

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2. COP (Computer Operating Properly) Reset

What it does: A COP reset is triggered by the watchdog timer when the software fails to service it in time.

Effect on ECC error:

- SRAM is not cleared

- ECC error persist: If the corrupted data is still in SRAM, the ECC logic may detect the same double-bit error again after reboot.

- Registers may retain values: Some registers may retain their values depending on the reset configuration.

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3. Recommendation

If you want to guarantee removal of ECC error conditions, use a POR reset. If you're debugging or recovering from a software fault and want to preserve memory for analysis, a COP reset might be more appropriate.

So, it is good to ensure RDY is checked and processed without RAM usage after POR.  If the system is restarted by COP then try to write to the word and check whether the ECC error is definite.

Best regards,

Ladislav