M9S12XET 256 - SPI - Slave output

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M9S12XET 256 - SPI - Slave output

Contributor I

Hello All,


I am getting crazy with such thing.......


I have connected SPI0 to SPI1 (MOSI, MISO, CLK, nSS) and configured the first as slave and the second as master. 125KHz B.R. and 8 bits of data.


First my master software sends 5 bytes of data to the slave. The transfer is successful! It uses interrupts SPIE.


Then the slave software writes the first of 4 bytes (to be sent to the master in reply) into the data register SPI0DRL (the value of this first byte is '65') and waits the master to drive the clock.


Before writing '65' into SPI0DRL, SPTEF is '1', after it is '0' steady. Honestly, I expected SPTEF to '0' only for short time.


Then the master drives the clock, by sending 4 dummy bytes to the slave.


The master receives correctly 4 bytes (interrupts occur correctly 4 times on both SPI0 and SPI1)  .....BUT the first byte received by the master has value '0', not '65' ! The other bytes are correct.


During the process the nSS is always low (slave selected).


Somebody can explain me?

Many thanks in advance eventually!

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Specialist III

Hello, and welcome to the forum.


In the absence of you posting your problem code, my best guess is that you have an overrun condition existing at the master end, when the first command response byte is returned.  It is possible that the SPIF flag is then cleared prior to each additional byte being received, so that further bytes are correctly read.


The master SPIF flag will become set when the sending of each byte has been completed, and should be cleared before sending the next byte to the slave, whether a command byte or a dummy byte.


You also need to ensure that there is sufficient time for the first byte of the returned slave data to be written to the data register, before the master commences to interrogate the data.  This may possibly involve an additional delay, depending on the amount of processing required at the slave.  Whilst the first byte is being returned, the slave may then write a second byte to the data register to ease timing issues, by making use of the double buffering capability.





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