Interrupt priority decoder

Showing results for 
Search instead for 
Did you mean: 

Interrupt priority decoder

Contributor V

Hi All,

I am referring the MC9S12ZVM-Family RM

In that Chapter 4.4.3 Priority Decoder has a NOTE.

Care must be taken to ensure that all exception requests remain active until
the system begins execution of the applicable service routine; otherwise, the
exception request may not get processed at all or the result may be a
spurious interrupt request (vector at address (vector base + 0x0001DC))

Can someone please explain what exactly  "care must be taken " here mean.

From a software point of view what exactly are the steps to be taken to ensure the exception request remains active.

Thank you in advance

Labels (1)
Tags (1)
0 Kudos
1 Reply

NXP TechSupport
NXP TechSupport


Typically spurious interrupts are caused when an interrupt source is masked at the same time the interrupt is asserted. The processor attempts to recognize the interrupt, but by the time it gets to the interrupt controller the interrupt has been masked, so the original source of the interrupt cannot be found.


Disabling a specific interrupt source without previously setting the I mask bit in the CCR can result in spurious interrupts which cause the micro-controller to take the spurious interrupt vector instead of the expected interrupt vector.


It is recommended to set the I mask bit before disabling a maskable interrupt source to avoid spurious interrupts.


A spurious interrupt occurs when the micro-controller starts interrupt processing due to an asserted interrupt, but when the interrupt vector is fetched, the interrupt has gone. In this case, the microcontroller will fetch the spurious interrupt vector.

 Interrupt flags must be cleared only within corresponding interrupt routines to be absolutely sure the spurious interrupt will not be generated

 Spurious interrupt is generated always the source of interrupt is not known => also problem can be in the case of IRQ and XIRQ, when they are level sensitive, they can be deactivated before the CPU recognize interrupt source => When IRQ or XIRQ are enabled the pulse connected to these pins have to have minimal given length to generate valid interrupt.


Moreover, you should check whether interrupt flags are correctly cleared.

For example: clear flag bit 3 in register PIFP:

PIFP = 0x08; // correct

PIFP |= 0x08; // wrong approach because this approach clears all flags in the PIFP register (not only selected) because process is made as read-modify-write.


Best regards,


0 Kudos