Hi All,
If I have one interrupt function
Type1 : Do something then clear interrupt flag
void interrupt ISR_XXX(void)
{
do something;
clear interrupt flag;
}
Type2: Clear interrupt flag and do something
void Interrupt ISR_XXX(void)
{
clear interrupt flag;
do something;
}
Which one is best? And could anyone help me to explain what difference between them?
Thanks
Regards,
Pogo Lin
解決済! 解決策の投稿を見る。
For example your ISR takes 100us. First variant allows to handle two events, which are 50us apart. It doesn't allow to keep handling events that come at 1/50us rate, but it may be important to clear flag at top of routine
2nd variant is kind of filtering too often events. Say your ISR still takes 100us, and you have burst of 3x 75us events. You handle first, ignore second, and you have a 2*75us -100us = 50us window to handle other ISR's.
There's no best, it depends on application.
For example your ISR takes 100us. First variant allows to handle two events, which are 50us apart. It doesn't allow to keep handling events that come at 1/50us rate, but it may be important to clear flag at top of routine
2nd variant is kind of filtering too often events. Say your ISR still takes 100us, and you have burst of 3x 75us events. You handle first, ignore second, and you have a 2*75us -100us = 50us window to handle other ISR's.
There's no best, it depends on application.
If I don't clear interrupt flag, when the next interrupt occurs would the interrupt function be called again??
Thanks~
Pogo Lin
If you don't clear interrupt flag, your interrupt will be called again and again, making software irresponsive. It doesn't make a lot of sense, even if you wish to keep looping in ISR handler for a while. Entry and exit from ISR takes some time, so it is better keep looping in ISR instead of wasting CPU cycles for extra SWI (similar operation like entry to ISR on HW interrupts) and RTI instructions cycle times.
Of course you should try avoiding long ISR's. In case something slow (a lot to do in ISR) has to be handled, interrupt nesting may be enabled. You enter your slow handler, immediately mask current interrupt (for example in case are servicing TIM/ECT ch.l 2, you mask it with TIE &= ~(1<<2); ), and reenable I-bit interrrupts with asm("CLI"). Then you keep servicing your slow interrupt, which can be interrupted by any other interrupts but not with by the same slow one. When you are about to exit, you may reenable disabled interrupt clearing interrupt flag first, and then unmasking disabled interrupt. Of course you still may decide to clear flag on entry to ISR to be able to service double events, though, if you may tolerate so slow delay, then peraphas it could be handler without interrupts in main() thread?