IIC or I2C SCL issue in s12x Dp512 controller

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IIC or I2C SCL issue in s12x Dp512 controller

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santhoshsl
Contributor III

Hello,

 

I am using S12x DP512 controller for our project.

In this I2C 1 has been configured to be used for getting data from Real Time Clock (ST micro electronics RTC ).

I did Initialization and wrote basic read and write code snippets. I was able to see the expected Pulses coming out of SDA line in sync with SCL.

But RTC expects data to be sent at 400kHz. But I am facing issue in getting this frequency.

 

I am using S12XDP512 evaluation board and following settings for clock

OSC_SEL = CRYSTAL -- 4MHZ

XCLKS#=0 - Connected

So this should ensure 4Mhz on board

 

And configured PLL to get 16Mhz as below

  CLKSEL = 0;

/* PLLCTL: CME=1,PLLON=0,AUTO=1,ACQ=1,FSTWKP=0,PRE=0,PCE=0,SCME=1 */

   PLLCTL = 177;

/* SYNR: ??=0,??=0,SYN5=0,SYN4=0,SYN3=0,SYN2=1,SYN1=0,SYN0=1 */

  SYNR = 5;                    /* Set the multiplier register */

/* REFDV: ??=0,??=0,REFDV5=0,REFDV4=0,REFDV3=0,REFDV2=0,REFDV1=1,REFDV0=0 */

  REFDV = 2;                   /* Set the divider register */

/* PLLCTL: CME=1,PLLON=1,AUTO=1,ACQ=1,FSTWKP=0,PRE=0,PCE=0,SCME=1 */

  PLLCTL = 241;                


   while(!CRGFLG_LOCK);   /* Wait until the PLL is within the desired tolerance of the target frequency */

   /* CLKSEL: PLLSEL=1 */

   CLKSEL = 128;

 

After this in IIC initialization, I am setting value of

IIC1_IBFD = 0x0B;   /* According to page 401 of controller spec */

this is to divide 16Mhz cpu clock to 400Khz.

 

But after doing all this I am getting a not seeing 400kh SCL on oscillator. Also the pulses i am seeing on Scope are saw tooth (for any frequency on SCL).

Can you guys help me in getting this 400Khz frequency for SCL.

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StenS
Contributor III

Your SYNR- and REFDV-settings will result in a 8MHz bus clock (PLLCLK = 2 * OSCCLK * (SYNR+1) / (REFDV+1) and Bus Clock = PLLCLK/2), and the IIC_IBFD in a SCL Divider on 40, resulting in a 200KHz IIC clock. But the RTC should still work, the 400kHz is a max frequency. You will have to find the reason for the sawtooth-formed signal in your hardware (do you have the required pullup-resistors on the SCL- and SDA-lines?).

/Sten


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RadekS
NXP Employee
NXP Employee

PLLCLK = 2xOSCCLKx((SYNR + 1)/(REFDV + 1))=2*4*(6/3)=16MHz

Bus Clock = PLLCLK/2 = 8MHz

Input clock for IIC module is Bus Clock.

So, settings if IIC Frequency Divider Register (IBFD) should be 0x00.

When you set Bus clock = 16MHz (SYNR=3, REFDV=0), you can use two settings for IIC with the same result IIC baud rate: IBFD=0x07 or IBFD=0x0B.

You can use IIC calculator in attachment.

Saw tooth will be probably caused by too big capacitance of your IIC bus or too big external pull-up resistors. Please check your I2C bus topology, board circuits and bus length according I2C specification:

http://www.nxp.com/documents/user_manual/UM10204.pdf

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santhoshsl
Contributor III

Thanks for those inputs. Yes it was external Resistance problem which caused this.

I could debug that issue.

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StenS
Contributor III

Your SYNR- and REFDV-settings will result in a 8MHz bus clock (PLLCLK = 2 * OSCCLK * (SYNR+1) / (REFDV+1) and Bus Clock = PLLCLK/2), and the IIC_IBFD in a SCL Divider on 40, resulting in a 200KHz IIC clock. But the RTC should still work, the 400kHz is a max frequency. You will have to find the reason for the sawtooth-formed signal in your hardware (do you have the required pullup-resistors on the SCL- and SDA-lines?).

/Sten


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santhoshsl
Contributor III

Thanks for those inputs. Yes it was external Resistance problem which caused this.

I could debug that issue.

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905 Views
santhoshsl
Contributor III

Can someone help me in this.

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