CW Pro v4.6
9S12DT256, mask 0L01Y
What would cause the IBB bit in IBSR to clear in the middle of a byte being transmitted?
I am trying to write to and then read and expansion port chip. I had been writing successfully but when I started to do the reads I noticed that my I2C bean function CheckBus() which is a macro for IBSR_IBB is clearing in the middle of a byte being transmitted. Because the RecvBlock function takes a pointer to a buffer I was calling that function and then trying to wait for the indication that a specified number of bytes had been received.
I need to write to the expansion port chip one byte address with write bit set and the number of the register to read as the second byte. Then I need to send the one byte address with write bit cleared (which RecvBlock() does) prior to receiving the number of bytes specified as a parameter to RecvBlock().
Here is the code:
byte error ;
byte receivedData[4];
word *bytesRead ;
destination = port ;
error = I2C1_SelectSlave( (byte)(destination + ADDRESS_BASE) );
IICCommand.asField.commandByte = INPUT_PORT_REGISTER ;
error = I2C1_SendChar(IICCommand.asField.commandByte);
// blocking while bus is busy
while(IBSR & IBSR_IBB) // or while(I2C1_CheckBus())
PORTE |= 0x04 ; // for debugging with scope
PORTE &= ~0x04;
error = I2C1_RecvBlock(receivedData, 1, bytesRead);
while(IBSR & IBSR_IBB)
PORTE |= 0x04 ;
PORTE &= ~0x04;
*data = receivedData[0] ; // *data is a parameter to this function
I have put a scope on SCL, SDA and on GPIO PE2 and watched this happen over and over. IBB should go high on a start condition and low on a stop condition and indicate a busy bus.