I'm having problems getting emulated EEPROM working on my HCS12.

[kennethjezek]

When running in the debugger it works every time. When not I find that 9 times out of 10 it powers up with the ACCERR bit set in FSTAT. When that happens EEPROM fails to work. I can clear the ACCERR bit by writing a '1' to it but it still won't work.

[kennethjezek]

I'll answer my own question. The ACCERR bit was being caused by a slow ramping of power to the micro. Adding a voltage monitor reset IC cured the problem. This is why it always worked in the debugger. It was fully powered when the debuggers reset took place. Other than this one bug the HCS12 worked fine. The emulated EEPROM (or maybe just FLASH in general) seems to be sensitive to how power is applied. If this bit is set during power up the HCS12 locks up at the first EEPROM memory access. Clearing the error has no effect.

[RadekS]

Hi Kenneth,

Could you please specify type (family) of your MCU and what you mean by “slow ramping of power to the micro” (some time constant or rather schematic could be useful)?

In fact any write to flash consumes some additional energy and higher load current typically means voltage drop. It is possible that your power supply was not sufficient to cover higher flash write current demands in initialization process.

I also already meet with flashing issue in case of too low capacity of blocking capacitor at VDD. Schematic says 470nF, but in fact board was assembled by only 470pF. That was not enough for covering changes in load current.

I hope it helps you.

Have a great day,
RadekS

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[kennethjezek]

The part number of the MCU is MC9S12XEQ512CAA. The board has a large number (25) of 68uF capacitors on board which limit how fast power can ramp up. VDD has a 10uF ceramic capacitor with 0.1uF in parallel. I've used this MCU on several other boards which also used emulated EEPROM without any problems running without a voltage monitor reset IC. In this case It sounds like the slow ramping of power combined with the transient increase in power demand caused by flash initialization was causing a problem.

[RadekS]

Hi Kenneth,

thank you for your details.

In case of S12XE family, Flash NVM should be powered trough VDDF voltage. The voltage supply of nominally 2.8V is derived from the internal voltage regulator.

VDDF pin should be connected only to external decoupling capacitor (220 nF, X7R ceramic).

Unfortunately VDDF is not routed to ADC, therefore we could not measure their value internally.

So, MCU will be fully powered in range of milliseconds, seconds,…?

There may be more reasons why ACCERR bit in the FSTAT register is set. For example if errors are encountered while initializing the EEE buffer ram during the reset sequence.

You said that clearing ACCER bit do not help even if MCU is already fully powered. Right?