HCS12XE XGATE Core 3?

[gnaws]

Hallo all,

I'm new to the HCS12XE processor, and have been messing around with it's XGATE capabilities recently.

In some of the code I downloaded, I see comments that are difficult to understand; e.g:

/* Two stacks in XGATE core3 */

#pragma DATA_SEG XGATE_STK_L

word XGATE_STACK_L[1];

#pragma DATA_SEG XGATE_STK_H

word XGATE_STACK_H[1];

  /* when changing your derivative to non-core3 one please remove next five lines */ 

  XGISPSEL= 1;

  XGISP31= (unsigned int)(void*__far)(XGATE_STACK_L + 1);

  XGISPSEL= 2;

  XGISP74= (unsigned int)(void*__far)(XGATE_STACK_H + 1);

  XGISPSEL= 0;

I've looked around in some documentation, but couldn't understand what the technical term "Core 3" means, and I don't completely understand what these lines of code are needed for.

Any help here, or explanation, would be quite useful

Thanks in advance for your time!

[HSW · Accepted solution]

There are two versions of the XGATE:

• The S12XGATEV2 (terminology of the reference manual), which is available on the S12XA, S12XB, and S12XD families
• The S12XGATEV3, which is built into the S12XE family.

The main difference between these versions is, that the S12XGATEV3 has two separate register banks (incl. R1-R7,  CCR, PC) for interruptable thread execution. This means that you also have two stack pointers (one for high and one for low priority threads) and therefore two stacks allocated in RAM.

[gnaws]

Thanks, I understand a little better now :smileyhappy: