HCS12 MSCAN identifier question

[prog_ram]

Hello,

I have a quick question about CAN identifier in HCS12 MCU.

When it says in some documents that the ID of the message is "23f" (I assume this is a hex), then:

1. is this means 0x023f or 0x23f0 ?

2. where is the first bit? is it left justified or right justified?

3. As the bits in the acceptance ID registers will be sorted from IDs0 to ID 28, Can anybody please

,as an example, tell me how would the four Acceptance registers look like when filled with the stated acceptance ID (23f)?

thank you,

[kef]

1. Message ID 23f should mean 0x023F. Least significant bit is ID0 bit. And location of ID0 bit depends on message format. If message is standard then ID0 is bit5 of register xxxIDR1. If message is extended, then ID0 is bit1 of register xxxIDR3. The id of received message, messageID is something like this:

unsigned long tmp;

tmp = *(unsigned long*)&CANRIDR1;

// is it extended message ?

// (IDE bit is bit3 of IDR1)

if(CANRIDR1 & (1<<3))

{

    messageID = (tmp >> 2) & 0x3FF80000ul;

    messageID |= tmp & 0x0007FFFEul;

    messageID >>=1;

}

else

{

    // no, it's standard ID

    messageID = (tmp >> (5+16) ) & 0x7FF;

}

2. So it depends where the first bit is. Search MSCAN docs for "Standard identifier mapping" and "Extended identifier mapping".

But when talking about id's, the numerical value of message id is just the numerical value of message id. For example message id of 0x124 means ID8=1, ID5=1, ID2=1 and all other IDx bits are 0.

3. 1) Acceptance registers have the same ID mapping like receive and transmit buffers.

2) CANIDAC register setup should tell how many acceptance filters you have and how many bits each filter is.

Since you are asking about 4 acceptance registers, I assume you are using 32bit acceptance filters and extended identifiers. If so then

CANIDAR0=0x23F >> 21;

CANIDAR1=((0x23F >> (15-2)) & 0xE0) | 0x18 | ((0x23F >> 15)&7);

CANIDAR2=0x23F >> 7;

CANIDAR3 = 0x23F << 1;

for RTR message please set CANIDAR3 bit 0.

And IDMR mask registers mapping is also the same.

CANIDMR0=CANIDMR1=CANIDMR2=CANIDMR3=0xFF; // this instructs to accept all messages

CANIDMR0=CANIDMR1=CANIDMR2=CANIDMR3=0; // this instructs to accept only message with ID, IDE and RTR bits matching IDAR0-3 registers

Hope it helps and doesn't confuse you further :smileyhappy:

[nandu]

HI Kef,

Thank you very much for your valuable answer. It is helpful to me . I got confused recently when i had to work on extended ID. It is cleared with your answer.

But, I just want to make sure with you one thing..

I think in the below sentance of your message, the register should be "CANRIDR0" instead of "CANRIDR1". May be it is a typing mistake.

>>unsigned long tmp;

>>tmp = *(unsigned long*)&CANRIDR1;

can you please confirm this
 

Message Edited by nandu on 2009-07-21 10:56 AM

[kef]

Nandu, you are right, it should be

   tmp = *(unsigned long*)&CANRIDR0;

and not

   tmp = *(unsigned long*)&CANRIDR1;

[nandu]

Thank you for the confirmation Kef

[prog_ram]

Great help Kef,

thank you.

take care.