External Bus ECLK Problem

[lgs]

Im working with a 9S12A256 Micro in expanded wide mode.  I've followed the example in AN2408, using an HC374 to decode the Address/Data Bus.  I'm trying to write to external memory at address $0400 and $0402.  From what I can see on the scope, the Timing of the write instruction (STD $0400) does not follow the spec for address hold time (2ns). 

Anyone else have this problem?  I've messed with clock stretching, but that doesn't do any good since the address is latched into the 374 on the rising edge of eclock. 

[lgs]

In addition, if I change the code to setup the micro in expanded narrow mode, the problem goes away.  That is, the address bus seems to hold properly before eclk rises.  In narrow mode, I have PEAR=$04, MODE=$A0.  In wide mode, PEAR=$04, MODE=$E0.  Also, I am booting up in single chip mode and writing to PEAR/MODE to change modes on startup. 

Maybe I'm missing something in the expanded wide mode setup.  This is our first application in 16-bit bus mode, we've been using 8-bit external busses for years.