Enhanced indexed addressing HCS12

[metboy]

Hi,
would you please tell me, why it is not allowd to use A14 and A15 (or A0 and A15?) to address the external device (external bus), when using the PortK pins (XADDR14...19) in Enhanced indexed addressing?
Thank you in advance!
metboy

[Steve]

In a nutshell this allows the external memory to see a linear address from the S12. The external memory would be addressed through the PPAGE window which is 16kbytes and so uses A0 to A13. A14 and A15 do not change in this window and so provide no useful information to the external memory. The XA address lines operate using the PPAGE value and so this tells the external memory which 16k block the S12 is addressing. Have a read of AN2287 which says the same thing but with pictures

[metboy]

Hi Steve,

thank you for the help!

i have just read the AN2287 and have got some question about conceptual interfacing in narrow or wide access mode:

How is it possible to address an external device with the addresses $0000 to $FFFF in narrow or wide with the address lines?

For example from the address $0000 to $03FF the internal registers are placed. They will be changed too or not?

should i use PPAGE? I've thought by paging, the address must be between $8000 and $BFFF.

Thank you in advace for your answer!

metboy

[imajeff]

It could be confusing but internal addresses are "mapped" to external address lines. Mainly, you might already see, accessing 0x8000 internally will not set up external address lines to be 0x8000, but rather A13..A0 will be 0x0000, and the other bank address lines (XA) will reflect whatever PPAGE is.

Because it's all mapped intelligently, accessing 0x03ff internally would not be mapped to external space, but would normally only map to the internal registers.

Message Edited by imajeff on 05-10-200611:26 AM

[metboy]

Hi imajeff,

thank you for the answer, but i don't understand the "Address Connection for MCU in Narrow Mode to One Byte- Wide Memory " ( Figure 3 in AN2287/D ).

All address lines are connected to the external memory, without paging. How does it work?

Thanks!

metboy

[Steve]

metboy,

 As imajef said,  this is just a conceptual drawing to help explain memory organisation. Don't treat it as a physical connection spec.

 Instead have a look in AN2408 which is the "how to wire it up" app note. (The topic was split over two app notes to separate the conceptual and practical aspects). This should help you sort out what you want to know.

[imajeff]

I think I see what you're asking. I should admit that I have not used expanded mode yet in 9S12 (only HC12), but I think the info is clear enough to explain.

First, that says it is conceptual, which means it is intended to demonstrate one concept, so might not show other concepts of the complete system. It is simplifying it by leaving out the PPAGE concept. They also leave out the fact that `lda 0` would by default access the PORTA register, not external memory.

Because the 16-bit address space (64K) does not use PPAGE, you would only have 64K of space (i.e. `lda $0000` to `lda $ffff`). I suppose that you could access external memory at all of these addresses, but you need to know that internally mapped space overrides external, and there are a few ways to get past this. Mainly, either move or turn off the internal block that is in the way. In other words, `lda 0` will not normally even try to retreive external mem because the hw register (PORTA) is still enabled and mapped there.

Look at Figure 2. This shows that in expanded modes, you might only find certain spots to access external mem, and perhaps only if you hold pin PK7 (ROMONE) low on powerup (to automatically disable internal Flash if booting from external mem).

I think one confusion might be how to tell whether you are accessing "near" addr (direct 64K) or "far" (using PPAGE). The best way I can tell is decoding the whole address. Since XADDR[19:14] directly indicate PPAGE contents, they can be used along with the low 14 bits of expanded bus ADDR[13:0]:

MCU         External Device
XADDR19  -- A19
...
XADDR14  -- A14
ADDR13   -- A13
...
ADDR0    -- A0

With these connections, the external address space is contiguous 1 Megabyte, but not internal method of addressing!

The intended method of addressing the first external byte above (0x00000) is

   movb #$00,PPAGE
   lda  $8000

That is not a "near" access. If you tried this

   lda  $0000

I assume you could get the same memory contents if PORTA was not mapped there, but there would be no way for external memory to distinguish between that and the 00:8000 address. Hopefully an expert will correct me if I'm wrong.

The solution is to add an external circuit to decode ADDR[15:14]. If it is (binary) 00, this is an access to "near" space. If 10, this is accessing the bank window in [0x8000..0xbfff].

I am actually not sure what happens with the fixed banks at $4000 and $c000. Are XADDR lines automatically set to access these?

See the MEBI reference guide for better details.

Message Edited by imajeff on 05-11-200611:21 AM

[imajeff]

I think this answers some but raises other questions about how PPAGE controls PORTK pins, from AN2287:

---

If the EMK bit in the MODE register is set, PPAGE values will be output on XADDR19–XADDR14 respectively (PORTK bits 5:0) when:

• The system is addressing within the physical program page window address space ($8000–$BFFF)
  
• The system is in an expanded mode

When addressing anywhere else within the physical address space (outside of the paging window), the XADDR19–XADDR14 signals will be assigned a constant value based upon the physical address space selected. For additional information refer to the HC12 and HCS12 CPU Reference Manual (Freescale Semiconductor document order number CPU12RM/AD).

In addition, the active-low emulation chip-select signal (ECS) will likewise function based upon the assigned memory allocation. In the cases of 48K byte and 64K byte allocated physical FLASH/ROM space, the operation of the ECS signal will depend additionally upon the state of the ROMHM bit in the MISC register. Again, this signal is only available externally when the EMK bit is set and the system is in an expanded mode.

---

(BTW I don't see anything in CPU12RMV4.pdf about XADDR stuff)

Those two conditions before outputing XADDR... Is that AND or is it OR?

It does indicate that PPAGE does not directly control XADDR[5:0]. If I `lda 0`, it apparently will not drive XADDR output from PPAGE because It's not within [0x8000..0xbfff]. The only advantage I see for that is that they stop me from using a larger bank window. Otherwise I could have used another addr bit (ADDR14) by doubling the window size. I could have used external addresses [00:000000..ff:1fffff], and had 2 MB of memory.

It does not mention what happens with XADDR and all 16 ADDR if I `lda $4000`. Does it output XADDR? The first part says it would not (only maps in $8000..$bfff), but that does not make sense according to all else.

Message Edited by imajeff on 05-11-200602:17 PM

[Steve]

imajef,

   I think you explained this quite clearly.

  You weren't sure of a couple of points:

   The XADDR lines were explained in the CPU manual but this section was later moved into the device databooks. It is now in the MMC section for each device.

   The value output on the XADDR lines for each address in the 64k map is in a table in the MMC section. This includes values for the fixed flash regions and the $0000 - $3FFF range.

[imajeff]

Steve, thanks for pointing out there is a new MMC document, but what do I refer to for my version, MC9S12DP256B? It is not listed.

And why do there seem to be more than one "S12MMCV4.pdf", rev 4.00, but different size files?

277k I already had
483.7k new download

Message Edited by imajeff on 05-12-200607:54 AM

Message Edited by imajeff on 05-12-200607:58 AM

[Steve]

Hi imajef,

   The DG256B manual says you need to refer to the "S12 Core User Guide". However, it looks like the original core guide has been pulled from the web. I'll get this sorted asap.

  The two MMCV4 documents are the same - the difference in file size is because the original was a Motorola document and the new one is Freescale (plus about 200k of pdf bloat)

[imajeff]

---

Steve wrote:

Hi imajef,

The DG256B manual says you need to refer to the "S12 Core User Guide". However, it looks like the original core guide has been pulled from the web.

---

Right. I'll appreciate seeing that "Core User Guide", as it has been missing for at least two years. Thanks.

[Steve]

Hi imajef,

  An interim update:

  The DG256B core block consists of the following modules: S12CPUV2, S12BDMV4, S12BKPV1, S12INTV1, S12MMCV4, S12MEBIV3. Right now we're looking at the best and quickest way of ensuring the documentation is clean going forward.