Hello,
Lundin wrote:For the reset itself, it needs a decoupling cap of around 47pF - 100pF. Larger caps like 100n will fail to give the steep edge on the reset that the S12 needs. And of course, you also need a pull-up on the reset line, and an external brown-out protection circuit (voltage supervisor of 4.6V or so) connected to the reset line, as DG256 doesnt come with internal LVD.
Surely the maximum allowable shunt capacitor value at the reset pin would depend on the external pullup resistor value used. If I were to assume a resistor value of 10k in conjunction with 100pF capacitor, the time constant would be 1 microsecond, giving a rise time of about 3 microseconds at the reset pin.
If it is possible to reduce the pullup resistor value to, say 1k, the capacitor value could be increased to 1nF for the same rise time. This could be beneficial in two ways - a much larger amount of induced energy to discharge the capacitor, and a higher amount of induced current to be maintained once the capacitor is partially discharged. Of course, the low voltage reset device would require to sink 5mA.
This assumes that the reset pin is the problem, and not some other reset source. If the interference is severe enough to affect the Vdd line, you will get a LV reset anyway.
Regards,
Mac