Yes and no. The XGATE is interrupt oriented RISC core independent from CPU. The only connection with CPU is shared RAM and common interrupts. Of course I have forgotten semaphores which can be used to avoid simultaneous access of the same variable from XGATE and CPU. So you are not able to run standard function from CPU but you can launch the same interrupt at CPU from XGATE.
The RM says:
10.5.2 Outgoing Interrupt Requests
There are three types of interrupt requests which can be triggered by the XGATE module:
4. Channel interrupts
For each XGATE channel there is an associated interrupt flag in the XGATE interrupt flag vector
(XGIF, see Section 10.3.1.8, “XGATE Channel Interrupt Flag Vector (XGIF)”). These flags can be
set through the "SIF" instruction by the RISC core. They are typically used to flag an interrupt to
the S12X_CPU when the XGATE has completed one of its task.
The example "XDP512-XGATE-SCI0_XGATEtoCPUisr-CW51.zip", I have attached, is not for XEP family but older 250nm XDP family device. The principle and commands are the same. Search for
asm SIF
instruction in the file xgate.cxgate. The instruction launches SCI interrupt at CPU from SCI interrupt at XGATE. This offers you to perform then what you want through this channel. Of course this is valid for each XGATE interrupt.
For more examples you can look at the set I put here a long time ago:
https://community.nxp.com/t5/S12-MagniV-Microcontrollers/LAMA-s-S12XE-unofficial-examples/ta-p/11007...
Best regards,
Ladislav
