Hi,
Could you please test folowing code and measure BUSCLK at PE4 pin?
Entire project is also attached. (CodeWarrior 5.1)
Note; BDM must be disconnected otherwise clock is affected by BDM connection and STOP mode does not work correctly
BR
Ladislav
//==============================================================================
// Note: USB BDM Multilink must be disconnected, otherwise it is not working
// because BDM affect behavior of the MCU and clock.
// OSCCLK = 16MHz; also setup for 8MHz is presented below
// BUSCLK = 16MHz; set by PLL
// BUSCLK is visible at pin PORTE_PE4
//==============================================================================
#include <hidef.h> /* common defines and macros */
#include <MC9S12XEP100.h> /* derivative information */
#pragma LINK_INFO DERIVATIVE "mc9s12xep100"
//==============================================================================
//==============================================================================
void set_pll(unsigned char _synr, unsigned char _refdv, unsigned char _postdiv);
void API_Init(void);
#pragma CODE_SEG NON_BANKED
interrupt 64 void API_ISR(void); // (0xFE-0x7E)/2 = 0x40 H = 64 d
#pragma CODE_SEG DEFAULT
//==============================================================================
void set_pll(unsigned char _synr, unsigned char _refdv, unsigned char _postdiv)
{
PLLCTL = 0B00000001; // CME=0,PLLON=0,FM1=0,FM2=0,FSTWKP=0,PRE=0,PCE=0,SCME=1
CLKSEL = 0B00000011; // PLLSEL=0,PSTP=0,PLLWAI=0,RTIWAI=1,COPWAI=1
SYNR = _synr; // Set the multiplier register
REFDV = _refdv; // Set the divider register
POSTDIV = _postdiv; // Set the post divider register
PLLCTL_PLLON = 1; // Enable the Phase Lock Loop
while(!CRGFLG_LOCK); // Wait till the PLL VCO is within tolerance
CLKSEL_PLLSEL = 1; // Select clock source from PLLCLK
ECLKCTL_NECLK=0; // Enable the BusClk output at ECLK pin (PE4) to see
// busclk if necessary; J102.15 (51) at EVB9S12XEP100
PLLCTL_FSTWKP = 1; // To enable fast wake up from stop mode
}
//==============================================================================
// API_Init
//==============================================================================
void API_Init(void)
{
VREGAPICL_APIFE = 0; //
VREGAPICL_APICLK = 0; //Autonomous periodical interrupt clock used as source.
VREGAPIR = 0xFFFF; //13107.2ms for APICLK=0
VREGAPICL_APIES = 1; //APICLK visible an connected to PTT_PTT5
VREGAPICL_APIEA = 1; //
VREGAPICL_APIE = 1; //API interrutp enable
VREGAPICL_APIFE = 1; //API enable
}
//==============================================================================
// API_ISR
//==============================================================================
#pragma CODE_SEG NON_BANKED
interrupt 64 void API_ISR(void) // (0xFE-0x7E)/2 = 0x40 H = 64 d
{
VREGAPICL_APIF = 1; //clear flag
}
#pragma CODE_SEG DEFAULT
//==============================================================================
void main(void)
{
unsigned int i,j;
// ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
DDRB = 0x0F; // PORT B0,B1,B2,B3 are outputs
PORTB = 0x00; // switch off diodes
// ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
API_Init();
// ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
set_pll(0x00, 0xC0, 0x00); // BUSCLK=16MHz from OSCCLK=16MHz
// set_pll(0x01, 0x80, 0x00); // BUSCLK=16MHz from OSCCLK=8MHz
// ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
asm ANDCC #$7F // enable STOP mode
// ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
EnableInterrupts; // enable I-bit maskable interrupts
// ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
for(;;)
{
asm STOP // STOP the MCU
for(j=0;j<100;j++)
{
for(i=0;i<0xFFFE;i++) asm nop; // SW delay
PORTB_PB3 = ~PORTB_PB3; // blink diode at PB3
// You can perform after STOP mode:
// 1) either
// if(j==4) // procedure to finish self clock
// { // mode and enable fbus=fosc/2
// PLLCTL_FSTWKP = 0;
// PLLCTL_FSTWKP = 1;
// }
// 2) and/or
if(j==32) // procedure to finish fbus=fosc/2
{ // mode and set and enable PLL
set_pll(0x00, 0xC0, 0x00); // BUSCLK=16MHz from OSCCLK=16MHz
}
}
}
// ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
}
//==============================================================================