The working code is here:
[Code]
| | // | Delay, pbd on, delay, pdb off |
| | delayLoop(20000000); | // | iterations / instr cycles to delay |
| | GPIOF_DR |= 0x40; | | // | Toggle bit 6 |
| | GPIOD_PER |= 0x80; | | // | PDB peripheral enabled. |
| | |
| | //PDB1_MOD = 50000; | | // | Modulus |
| | //PDB1_DELAYA = 1; | | // | 500us |
| | //PDB1_DELAYB = 45000; | // | 45us |
| | |
| | //delayLoop(10000); | | // | ~100ns per iteration: 10k = 1ms |
| | PDB1_MCTRL |= PDB1_MCTRL_PDBEN_MASK; | // | Switch on |
| | PDB1_MCTRL |= PDB1_MCTRL_SWTRIG_MASK; | // | SW trigger |
| | |
| | delayLoop(20000000); | // | iterations / instr cycles to delay |
| | GPIOF_DR &= ~0x40; | | // | Toggle bit 6 |
| | GPIOD_PER &= ~0x80; | | // | peripheral disabled. |
| | PDB1_MCTRL &= ~PDB1_MCTRL_PDBEN_MASK; | // | Switch off |
[/Code]
The code in the previous post has extra lines added in to disable the PDB before enabling, and spacing asm NOPs, as the original two lines enabling the module and setting the software trigger just didn't work.
The configuration is set in processor expert, and works for the above config, but not the previous post.
The requirements are that the PDB module remain logic one normally, but generate negative pulses, at approx 98% duty cycle for a period, every so often.
So, I've