About ATD

[zy]

Hello everybody!

I am using XET256 ATD, I had some problems. 

In MC9S12XEP100 Reference Manual,It said the ADC module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3.Refer to device specification for availability and connection of these inputs! I can't find device specification,and I don't know which pin can be use as ADC trigger input?I want a detailed document about ATD trigger.

I don't understand about left justified and right justified .reffer to the  attachment picture1, DJM seems affect the ATD conversion result register in  Figure 13-14 and Figure 13-14,but in table 13-22,12-bit data always store in ATDRRn bit11:bit0, please tell me which table is correct?

sorry about my poor english.

[kef]

See in Reference Manual;

1.7 ADC0 configuration  and

1.8 ADC1 External Trigger Input Connection

I think that purpose of table 13-22 is to reuse figures 13-14 and 13-15 for 10 and 8 bit formats. Instead of doing additional 4 pictures, they decided to add table 13-22. Meaning of 12bit - DM = X is that you don't have to remap your 12bit result since there are only 12 bits on figure 13-14 and only 12 bits on figure 13-15. It would be much clearer to have 6 pictures for all possible combinations of resolution and DJM.

[zy]

Thanks . I mean in table 13-22，I think ATDDRn's bit[15:12] will never be used ,no matter 8 bit, 10bit or 12bit result. ,but in figure 13-14 (when DJM=0) ,I think 12 bit result will use ATDDRn's  bit[15:4],  what's wrong of my understanding?    

And if ETRIG0 is TIMIOC1/MOSI1/PWM1/KWP1/PP1, and ETRIG1 is TIMIOC3/SS1/PWM3/KWP3/PP3? but ETRIG2 is Periodic interrupt timer hardware trigger 0, where is Periodic interrupt timer hardware trigger 0?  Periodic interrupt timer have no external pins, how can they become hardware trigger ,and have falling edge or rising edge? 

[kef]

No, the DJM means left or right justified format. In all bitness modes it is the same. In left justified mode all result bits are shifted left so that MSB of result is in MSB of 16 bits wide result register. In right justified mode LSB of result is in LSB of 16 bits wide result register. In right justified modes, top value of result register is 0x00FF for 8 bit mode, 0x03FF for 10bit mode and 0x0FFF for 12bit mode. In left justified mode you should get 0xFF00, 0xFFC0 and 0xFFF0 respectively for 8, 10 and 12 bit modes.

ETRIG0 to ETRIG3 are external for ATD module, but these are internal MCU connections. How they are connected is specified in above mentioned tables. For triggering MCU from external pin refer to table 13-6. Each ATD input pin can be can be used as an external ATD trigger.

[zy]

Thank you very much