9s12x ram decode

[michaelhuslig]

Many years ago, I abandoned a project using an early 9s12xa512 uP.  Recently I have started a new project using the 9s12xe uP and porting a good chunk of the original code.  But I noticed a lot of the code is accessing the internal RAM using global instructions with GPAGE=0.  I no longer have the original uP reference manual for the 9s12xa, but I remember the code working back then.  The only explanation would be if somehow I knew that the internal RAM is replicated/duplicated as multiple images between 00_0000 and 0F_FFFF caused by incomplete decoding of the upper address lines.  Does anyone know if this is the case?

Mike Huslig

[lama]

Hi,the manual is still accessible on our pages..and attached. As you know the memory in the S12X devices is possible to be accessed by different ways either in 16 bit addressing mode or 24bit addressing mode where the paging is used.

Gpage addrssing is able to cover entire address space of the MCU. Please look at the part of the memory map of the S12XE device...entire memory map is attached together with maps for mor S12XE devices. As you can see GPAGE 0 together with assemebler instructions for global load and global store accessing Register space and external memory space (external bus access, EBI module...https://community.nxp.com/docs/DOC-93594 ) in the case the device is used in expanded mode.....and no, there are not duplicated memory spaces. There is only a possibility to access one memory space in different ways.

Best regards,

Ladislav

[michaelhuslig]

Thank you.  As usual I wasn't thinking it through. I was using CS3 to

access external RAM with GPAGE=0, not internal RAM.  Sorry.