9S12XS128 - 64 pins socket and 16 channels ATD

[huguesangelis]

Hi all.

I'm writing courses (in french) for my students about the ADC12B16 of the 9S12XS128 in 64 pin LQFP.

I've got few questions to ask :

First of all : what will I get if I start a conversion on one of the unconnected pins (channels 8 to 15) ?

Next : what happends if I use a 16 channels sequence plus a WRAP around after channel 7 and activate the Compare on channels 8 to 15. Will I do a conversion of channels 0 to 7 (stored in data registers ATDDR0 to ATDDR7) and then do a comparaison of channels 0 to 7 with data stored in ATDDR8 to ATDDR15 ?

And last : What is the good formula to get the duration of a single channel conversion ?

For me the answer of the last question is :

duration = (nb of bits + 2 + sample time (defined by bits SMPx) + 2 * SMP_DIS) * Tatd.

Am I true ?

Thanks a lot to all.

[iggi]

Edward, i agree with you for the first two answer. Yes, it's true.

Just an important note from S12G reference manual (S12G features the same ATD module):

  n is conversion number, NOT channel number!

However, I also think a sequence should be of 2,4,8 or 16 conversions, it's easier to determine where could be the conversion result (or which CMPE bit to use for automatic comparison) and also in FIFO mode result register counter wraps around at the end (it's valid for continous scanning, SCAN=1).

Concerning the 2nd sequence in FIFO mode, it's quite tricky. If CMPE1 is set, ATDDR4 result register need to be checked if there is written result of 2nd conversion of (2nd) sequence, or ATDDR4 should be written with compare value and see the behaviour of CCF4 flag. CCF[n] is related with CMPE[n], CMPGT[n] and ATDDR[n]. So, it seems like if CMPE[1] is set, it concerns only ATDDR[1].

Hopefully, i am not wrong.

[huguesangelis · Accepted solution]

I finaly found an answer to my question in FIFO bit definition :

"If this bit is one, automatic compare of result registers is always disabled, that is ADC12B16C will behave as if

ACMPIE and all CPME[n] were zero."

So it's impossible to have both FIFO and compare...

It still remain the problem of FIFOR witch is set (in FIFO mode) at the end of the first sequence without any data lost...

I'm trying to see what chip simulation will tell me.

[kef]

Ivan, I'm unable to follow this:

• Just an important note from S12G reference manual (S12G features the same ATD module):
•   n is conversion number, NOT channel number!

It is not clear to me where I mentioned channel number instead of conversion number.

[iggi]

Well, you mentioned 2nd 3-channel sequence which make sense if Multi-Channel Sample Mode is enabled (MULT=1) when

the ATD sequence controller samples across channels.

I think this case is one channel for entire conversion sequence.

[kef]

I think that in last messages we were discurring 3 channels in FIFO mode, not one channel. From huguesangelis messages:

• - If I use FIFO mode with compare what is the right register to compare with ? For example if I use a conversion sequence of **3**, in FIFO mode...

• Therefore in a sequence of ***3*** conversions, it will use CMPE0 to CMPE2, regardless of the channels and regardless of the number of previous sequences.

• In FIFO mode, datas are stored in consecutive result registers, so the first sequence will use ATDDR0, 1 and 2. The second one (kef: sequence of 3 channels conversion) will use (without comparison) ATDDR3, 4 and 5

[huguesangelis]

A great thank for the formula its now part of my course (Who shall I do credit).

But still another questions rised in my silly mind :

- If I use FIFO mode with compare what is the right register to compare with ? For example if I use a conversion sequence of 3, in FIFO mode, and I want to compare the second element of the sequence, if I activate CMPE1, the first sequence should work, but what about the second sequence ? As they say that CMPE identified the conversion number of a sequence, but also compares it with register ATDDRn where n is the convertion number of the sequence ?

Thanks one more time to you and to Edward Karpicz (sorry I ain't look so far in the datasheet to see that the answer was here. Sorry).

Greetings

[iggi]

Hi,

I was trying to understand your question and hopefully i did. So i believe the information below make sense:

- Concerning the register to compare, it is ATDDR.

ATDDRn should be written with the compare value (e.g. 0xFF). However, this register is used to store the conversion result as well. But, in case if automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), and ATDDRn holds the compare value you wrote there, then the conversion result will not be stored there at the end of the conversion but is lost.

Moreover, compare is always done using all 12 bits of both the conversion result and the compare

value in ATDDRn. Refer to chapter ATD Conversion Result Registers (ATDDRn)

- When FIFO mode is enabled, conversion results are placed in consecutive result registers (wrap around at end).

So in your case of conversion sequence of 3, the second sequence should be written to ATDDR3/4/5 regsiters. If you want to use automatic compare, then e.g. activate  CMPE4=1, Write compare value to ATDDR4 result register and Write compare operator with CMPHT[4] in ATDCPMHT register. Then CCF[4] in ATDSTAT2 register will flag a success of any comparison.

- CMPE bits enables automatic compare of conversion resluts. If a bit is not enabled, for example CMPE2=0, then ATDDR2 is written with conversion result.

Cheers,

Ivan

[huguesangelis]

Well thank for your answer. But I'm still doubtful, maybe I don't understand the datasheet, so I will try to expose you my thinking step by step.

CMPE bit are defined in the datasheet as : "Compare Enable for Conversion Number n (n= 15,..., 0) of a Sequence".

Therefore in a sequence of 3 conversions, it will use CMPE0 to CMPE2, regardless of the channels and regardless of the number of previous sequences. Am I true ?

And furthermore it's written that :

"For each conversion number with CMPE[n]=1 do the following:

1) Write compare value to ATDDRn result register"

So for CMPE1, the comparison will use ATDDR1 and ATDCMPHT1 regardless of the channels used and of the number of previous sequences. Still true ?

In FIFO mode, datas are stored in consecutive result registers, so the first sequence will use ATDDR0, 1 and 2.

The second one will use (without comparison) ATDDR3, 4 and 5, but as CMPE1 is set, register used should be : ATDDR3, ATDDR1 (for comparison) and ATDDR5 (or ATDDR4, here the datasheet lack of informations, but I think that looking at CC bits of ATDSTAT0 will give me the answer) and so on.

So now if I carry on with my conversions sequence, the 6th sequence will use data registers : ATDDR15, ATDDR0 and ATDDR1, without comparison, and with the comparison, the registers ATDDR15, ATDDR1 (for comparison), ATDDR1 (for conversion result).

And if I carry on, the 12th sequence will use registers ATDDR1 to ATDDR3 without the comparison and with the comparison : ATDDR1 (for conversion result), ATDDR1 (for compaison) and ATDDR3...

The last case is the worst and is almost impossible to prevent... I mean that it's not a meaning of programmation, it's a hardware issue.

I hope that you will understand me (and not bored you too much).

Greetings to all.

H. Angelis

[kef]

• Therefore in a sequence of 3 conversions, it will use CMPE0 to CMPE2, regardless of the channels and regardless of the number of previous sequences. Am I true ?

I think so

• So for CMPE1, the comparison will use ATDDR1 and ATDCMPHT1 regardless of the channels used and of the number of previous sequences. Still true ?

Yes

For 2nd 3-channels sequence in FIFO mode CMPE1 is irrelevant. You need to set CMPE4 to compare the same AD channel.

I think that FIFO mode makes sense only for N-channels FIFO, where 16/N is integer. 1, 2, 4, and 8 channels FIFO make sense, since the same ATDDRx result / compare register will be used with the same channel.

[RadekS]

Just few details:

• First of all : what will I get if I start a conversion on one of the unconnected pins (channels 8 to 15) ?

In most cases you will get value around zero, but generally you can get any value from ATD range.

• And last : What is the good formula to get the duration of a single channel conversion ?

For me the answer of the last question is :

duration = (nb of bits + 2 + sample time (defined by bits SMPx) + 2 * SMP_DIS) * Tatd.

As it was correctly mentioned, your formula didn’t fit to table Table A-14. ATD Operating Characteristics (Reference manual - page 673). We can modify your formula to:

duration = (N + sample time (defined by bits SMPx) + 2 * SMP_DIS) * (1/ fATDCLk).

Where N = 13 for 8bit conversion, N = 15 for 10bit conversion and N = 16 for 12bit conversion

[kef]

• First of all : what will I get if I start a conversion on one of the unconnected pins (channels 8 to 15) ?

Hm, you will get conversion of unconnected pin.

• Next : what happends if I use a 16 channels sequence plus a WRAP around after channel 7 and activate the Compare on channels 8 to 15. Will I do a conversion of channels 0 to 7 (stored in data registers ATDDR0 to ATDDR7) and then do a comparaison of channels 0 to 7 with data stored in ATDDR8 to ATDDR15 ?

I think that's right.

• And last : What is the good formula to get the duration of a single channel conversion ?
• For me the answer of the last question is :
• duration = (nb of bits + 2 + sample time (defined by bits SMPx) + 2 * SMP_DIS) * Tatd.

Did you see A.2.1 ATD Operating Characteristics, table item #8 and note 3? Difference between 8 and 10 bits conversions is 2 ATD cycle, while diff 10 vs 12 is just 1 ATD cycle. It doesn't agree with your formula.