9S12XDP512 - Spurious interrupt

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9S12XDP512 - Spurious interrupt

Contributor I


I'm have a problem with spurious interrupt in a 9S12XDP512 processor.

I have two interrupts that some times occurs at the same time (XINT and PIT1).

Looking with the scope I realized that when they occur at the same time XINT ISR is runned and the PIT1 ISR gives me a spurious interrupt.

What can I do to make the processor run the PIT1 ISR after it ends the XINT ISR?

Alban Edit: Part number in subject line.

Message Edited by Alban on 2007-03-26 01:18 PM

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Contributor I
What should happen is the XINT interrupt should be called by the hardware and set the I bit in the CCR.  This will prevent all maskable interrupts.  The XINT ISR should end with a rti instruction which will restore the previous state of the CCR.  If the I bit was clear before the XINT interrupt, it should now be clear, and the PIT1 interrupt should be taken.
You should be able to monitor the state of the I bit through this process by placing breakpoints.
Are you clearing the I bit in your startup code to enable interrupts?
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