9S12GC16 EMI Problem

[ttian]

Hi,

I design a dashboard and do EMI test.

The EMI biggest noise points are 49.152MHz，73.728MHz、98.304MHz.

The bus clock of MCU is 24.567MHz. It's 2, 3, 4 times of bus clock.

the capacitor C19(0.1uF) is one capcitor between VDDPLL and VSSPLL.

When I removed C19, the cluster passed the EMI test.

But I found the system is not stable without C19.

The question is C19 could be removed during production? Is there any risk if removing C19?

I will change Colpitts oscillator to Pierce type and PE7 is connected to VDD to see if this has influcen for EMI.

Do you have any suggestions how to reduce EMI?

[Alban]

Ni Hao,

Decoupling is necessary to ensure the PLL has enough power when needed.

Improving thr oscillator layout is a better option.

What are the value of these noise peaks ?

The peaks are normal because are harmonics of the bus clock. But their values can be controlled with layout and other considerations (slew rate, no 90° angles on PCB...)

祝好,

Alban.

[ttian]

xiexie!(Thank you!) the problem has been solved by changing PCB layout.