p2020 RDB REV register setting to use ICE

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p2020 RDB REV register setting to use ICE

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yehudamarko
Contributor I

can you provide with registers setting for ICE / code warrior for the following board , P2020RDB REV C .

I have difficulties to set the DDR regs

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yehudamarko
Contributor I

Yes, on bottom side of PCB there is a sticker with only one line: SCH-21802 REV D.

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ufedor
NXP TechSupport
NXP TechSupport

The SCH-24802 has DDR2 SDRAM, so it is needed to use P10xx-P20xxRDB_P2020_init_core.tcl

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ufedor
NXP TechSupport
NXP TechSupport

On the PCB there should be a sticker containing two lines one of which is "SCH-nnnnn REV x".

Please provide information from this sticker.

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188 Views
yehudamarko
Contributor I

did you attach any file of the regs setup, ?

I don't see any file attached

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ufedor
NXP TechSupport
NXP TechSupport

No.

> but uboot is running from DDR , so ddr is working.

U-Boot is running from the L2 SRAM.

CCSR base address is 0xFFE00000

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188 Views
yehudamarko
Contributor I

I see now --- no prompt.

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yehudamarko
Contributor I

but uboot is running from DDR , so ddr is working.

can you provide the CCSBAR adrs defined while uboot is running.

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ufedor
NXP TechSupport
NXP TechSupport

> but uboot is running from DDR , so ddr is working.

U-Boot is running from the L2 SRAM.

CCSR base address is 0xFFE00000

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188 Views
yehudamarko
Contributor I

P2020RDB-PA REV G (u-boot prints RevC)

CPU 1000 MHz

DDR 667 MHz

CPU REV 1.0

TDA3474

This is the output from u-boot – it does not continue past last line, i.e. no prompt:

----------------

-Boot 2011.12-00064-gbfb0c9a (Oct 09 2012 - 20:52:46)

CPU0:  P2020E, Version: 1.0, (0x80ea0010)

Core:  E500, Version: 4.0, (0x80211040)

Clock Configuration:

CPU0:1000 MHz, CPU1:1000 MHz,

CCB:500  MHz,

DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:31.250 MHz

L1:    D-cache 32 kB enabled

I-cache 32 kB enabled

Board: P2020RDB RevC

(36-bit addrmap)

I2C:   ready

SPI:   ready

DRAM:  Configuring DDR for 666.667 MT/s data rate

----------------

How do I get the DDR registers? How do I derive the address where they are mapped?

Thank you

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188 Views
ufedor
NXP TechSupport
NXP TechSupport

In this case it could be assumed that the DDR SDRAM is damaged.

Please use a debugger to check the DDR controller registers settings in the problem state.

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ufedor
NXP TechSupport
NXP TechSupport

Please note that if the board is bootable, than it is possible to ptint the DDR controller registers by the 'md' U-Boot command:

Please provide information from all on-board inscriptions and sctickers.

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