enable/disable CoreNet Platform Cache in P2041

[ronaldw]

I am seeing a discrepancy in performance on 2 P2041 boards. We think it might be because one has its CoreNet Platform Cache disabled.

How can I read the status? Alternately, how can I enable/disable the CoreNet cache?

[ufedor]

By default CPC is initialized and enabled by U-Boot in the "cpu_init.c":

u-boot/cpu_init.c at b3f98d438eefd1b355efdec0b50af5813ff8d0e1 · qoriq-open-source/u-boot · GitHub 

The CPC status can be inspected by reading the CPC_CPCCSR0 - refer to the QorIQ P2040 Reference Manual, 8.2.1 CPC configuration and status register 0 (CPC_CPCCSR0).

Please provide ZIP package containing U-Boot and Linux booting logs for bot boards as attachment.

[ronaldw]

Thanks. From this, I was able to confirm that one of the boards had its CPC disabled.