cache locking instructions

[walter95]

Hi,I would like to use the cache line locking instructions (like dcbtls or dcblc) on nxp t1040 platform and I was wondering: how these instructions impact the allocation of data in the shared cache?

[andrei_skok]

A detailed description of these instructions can be found in the following documents:

Programmer's Reference Manual for Freescale Power Architecture Processors
https://www.nxp.com/webapp/Download?colCode=EREF_RM

e5500 Core Reference Manual with Updates - Reference Manual
https://www.nxp.com/webapp/Download?colCode=E5500RM

[walter95]

I know these manuals and I think I have read almost everything that interested me, but I don't think I have found anything regarding the impact of data allocation of these instructions