We are using LS1043A in our System. I need to Set the RCW configuration for 509-511 (HWA_CGA_M2_CL K_SEL) Hardware accelerator block cluster group A Mux 2 clock select.

[logeshs]

We are using SD card, and for running that we have decided to use the Platform Clock through the register ESDHCCTL[PCS]. 

1. Now what value should i select in this field RCW[HWA_CGA_M2_CLK_SEL]?

2. If in case we wanted to use the Peripheral clock then i have another doubt. In the QorIQ LS1043A Reference Manual, Rev. 1, 08/2016 in RCW configuration of 509-511 (HWA_CGA_M2_CLK_SEL) two illustrations were explained with eSDHC and eSDXC. In both illustration Net Result frequency is obtained after dividing by 6. Does this 6 corresponds to 7-4(DVS), Base Clock divisor explained in SYSCTL_ESDHCCTL_CRS_0? or Say I'm running my PLL2 at 1.5GHz Explain me how to achieve 50MHz for SD card operation?

[ufedor]

1) As referenced in RM, 001 – for CGA1PLL2, divide by 1 and  011 – for CGA1PLL2, divide by 3

2) There are two dividers in eSDHC module, controlled through SDCLKFS and DVS (as explained in SYSCTL_ESDHCCTL_CRS_0). Prior to that there is a fixed dividor (divide by 2). This divider divides only the clock sourced from PLL (not on platform clock). Please refer to 20.4.4.1 “Clock generator” (Base clock can be selected by programming ESDHCCTL[PCS]. It selects between platform clock and peripheral clock / 2. Base clock is divided by two of peripheral clocks when PCS=1).

The incoming clock is first divided by DVS and then SDCLKFS.

The "6" divider value is split between "fixed divider -peripheral clock / 2" and  divide by 3 in DVS (2x3=6).

> Say I'm running my PLL2 at 1.5GHz

> Please explain how to achieve 50MHz for SD card operation?

PLL2 @ 1500 MHz. This implies peripheral/2 = 750 MHz. set DVS to 1110 (divide by 15) and SDCLKFS to 00000000 (base clock). 750/15 = 50 MHz.

[logeshs]

Thanks for your comment,

So now i got a clear understanding on the Question 2.

But for Question 1 - you mean to say that we can choose any value in 509-511 (HWA_CGA_M2_CLK_SEL) if i use Platform clock as base clock for generating SDHC_CLK? 

Also please confirm my implementation. I'm keeping my Platform Frequency to 400MHz and through ESDHCCTL[PCS] register I'm choosing platform Clock(400MHz) for generating SDHC_CLK (50MHz). So I'm setting DVS to 0111 (divide by 8) and SDCLKFS to 00000000 (base clock). So 400/8 =50MHz (Platform clock/8 = SD_CLK).

[ufedor]

> For Question 1 - you mean to say that we can choose any value in 509-511

> (HWA_CGA_M2_CLK_SEL) if i use Platform clock as base clock for generating SDHC_CLK?

Yes.

The clock frequency calculation is correct.

[logeshs]

I also have doubt in setting RCW  value for bits MEM_PLL_RAT(10-15) which is used to select DDR Clock. In datasheet in table 159 it is mentioned as the ratio  between DDR datarate: DDRCLK ratio, but in Reference Manual It is mentioned as the ratio between DDR PLL:SYSCLK Ratio. 

My Core Freq is 1.6GHz, Platform Freq is 400MHz, and DDR Data rate need to 1600MT/s. Kindly help me what value should i keep in MEM_PLL_RAT(10-15) RCW setting?

[ufedor]

Please create new thread.

This will be convenient.