V.35 implementation

[ibram]

Hi,

We are trying to implement V.35 interface by using P1021 QUICC Engine's UART. I believe V.35 requires Transmit and Receive Clock and  I was unable to find out the pins for TXCLK and RXCLK from the UART. Can you please direct me with the pin details or suggest the alternate way of implementing it.

Thanks and Regards,

Ibram

[LPP]

P1021 QE UCC UART can be configured to synchronous mode.

The clock source options for the serial controllers for P1021 are shown in QEIWRM Rev.5 Table 5-6. "Clock Source Options—External Clock Signals (P1021, P1012, P1025, P1016)" or P1021RM Table 22-4. "Clock source options-external clock signals"

For example, you can configure UCC5 to use  CLK13 as RXCLK and CLK15 as TXCLK. Further, these signals should be enabled via parallel port configuration. P1021RM Table 3-8: pin PB11 as CLK13, pin PB31 as CLK15.

Have a great day,
Pavel

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[ibram]

Hi Pavel,

Thanks for your response.

I am planning to use UCC1 UART for this interface. Below are the Pins and signals details. Could you please verify the same?

Pin Name	Signals name
PA7	SER1_TXD[0]
PA6	SER1_RXD[0]
PA4	SER1_CTS
PA5	SER1_RTS
PA8	SER1_CD
PA24	RXC - CLK9
PB1	TXC - CLK10

Also there are some more signals missing for V.35, like Transmitted data timing, DTR, DSR.

How do we handle these signals?

Thanks in Advance..

Regards,

Ibram

[ibram]

Hi,

Do I have any updates?

Regards,

Ibram