T4240 NOR Boot

[chengdang]

We designed a custom board with T4240. During power on, T4240 reads RCW data, PBI data from EEPROM. In RCW boot location is mentioned as IFC and 128 MB NOR flash is connected to CS0.

After reset its not booting the u-boot in NOR. Chip select is not coming from T4240.

HRESET is released,ASLEEP goes low. PBI data is reflected in CCSR registers.But not booting from NOR. Program counter is in 0xFFFFFFFC(Observed through JTAG).

Any ideas why its not loading boot blocks from NOR...

[monalihaware]

Was your issue solved?

[madhurashetty]

Cheng dang,

Please specify are you using 16-bit/32-bit NOR Flash

Regards

Madhura

[chengdang]

We have changed RCW source to IFC NOR instead of I2C and we found that T4240 not driving chip select0 to read RCW values from NOR flash. The IFC chip select 0 is always high after releasing the PORESET and HRESET is low.

If we keep RCW source to I2C, T4240 reads RCW values, releases HRESET but not loading U-boot from IFC NOR though we kept boot location as IFC NOR flash. NOR flash is connected through CPLD, CPLD performs the address latching. We are able to read/write to NOR flash through JTAG. 

[chengdang]

We probed the below signal with respect to PORESET and found they all are driven high during PORESET deassertion.

IFC_AD17 to IFC_AD20, IFC_AVD,IFC_CLE,IFC_OE_B,IFC_WE0_B,IFC_WP0_B.

All the above signals have pull-ups except IFC_AD17 to IFC_AD20. Along with pull-up resistor they are driven high by CPLD.

[ufedor]

Please provide for inspection values of all DCFG_CCSR_RCWSRn registers.

You wrote:

> Program counter is in 0xFFFFFFFC

What is the data value at this address?

[chengdang]

Attached the register dump T4240. Register dump is collected through JTAG in Attach mode without JTAG reset. Also attached the screen shot of disassembly, reset vector data.

NOR flash is connected through CPLD, CPLD performs the address latching. We are able to read and write to NOR flash through JTAG. After programming we verified the u-boot contents in the flash. 

[ufedor]

Please use a digital scope to ensure that all signals having note 5 in the QorIQ T4240 Data Sheet, Table 1. Pinout list by bus have high levels when PORESET_B is asserted.

[chengdang]

When we connect the emulator through Attach mode without JTAG reset, the pc is in 0xFFFFFFFC and if i tried to run step by step, t4240 not steps out of 0xFFFFFFFC. Even if i change, the PC to 0xFFFFF000 and execute, t4240 not steps out of 0xFFFFF000. Able to view the u-boot contents in flash .

When we connect the emulator through download mode with JTAG reset.  if i change the PC to 0xEFFFFFFC(flash u-boot location)  i am able to execute step by step until it reaches 0xeff40960. Once again it not steps out of 0xeff40960.

We observed HRESET_B is released high, ASLEEP goes low and no RESET_REQ_B assertion. So T4240 comes out of POR sequence successfully.  Is our understanding is correct on this point.

[ufedor]

Please use a digital scope to ensure that all signals having note 5 in the QorIQ T4240 Data Sheet, Table 1. Pinout list by bus have high levels when PORESET_B is asserted.